Samsung Electronics Co., Ltd.

Si-Hyung Lee

Dong-Suk Shin

Jeong-yun Lee

Yeong-Jong Jeong

Geo-Myung Shin

Seo-Jin Jeong

Si-Young Choi

Ki-Hyun Hwang

Dae-Ik Kim

Dongsoo Woo

Ho-Jun Lee

Myoung-Bum Lee

Suk-Hun Choi

Jong-Ryeol Yoo

Ho-in Ryu

Ji-Young Min

Sang-Ryol Yang

Sangbom Kang

In-Sang Jeon

Heedon Hwang

Shi Li Quan

Dae-Young Jang

Shi Ii Quan

Bong-Su Kim

Yu-Ghun Shin

A semiconductor device and a method of fabricating the same are provided. The semiconductor device comprises a first multi-channel active pattern which is defined by a field insulating layer, extends along a first direction, and includes a first portion and a second portion; a gate electrode which extends along a second direction different from the first direction and is formed on the first portion; and a first source/drain region which is formed around the second portion protruding further upward than a top surface of the field insulating layer and contacts the field insulating layer, wherein the second portion is disposed on both sides of the first portion in the first direction and is more recessed than the first portion, a top surface of the first portion and a top surface of the second portion protrude further upward than the top surface of the field insulating layer, and a profile of sidewalls of the second portion is continuous.

Semiconductor device and method of fabricating the same

A semiconductor device includes a first multi-channel active pattern defined by a field insulating layer and extending along a first direction, the first multi-channel active pattern including a first portion having a top surface protruding further in an upward direction than a top surface of the field insulating layer and a second portion on both sides of the first portion, the second portion having sidewalls with a continuous profile and a top surface protruding further in the upward direction than the top surface of the field insulating layer and protruding in the upward direction less than the top surface of the first portion, a gate electrode on the first portion of the first multi-channel active pattern and extending along a second direction different from the first direction, and a first source/drain region on the second portion of the first multi-channel active pattern and contacting the field insulating layer.

Integrated circuit devices including Fin field effect transistors (finFETs) and methods of forming those devices are provided. The methods may include forming a fin on a substrate and forming a gate line on the fin. The method may also include forming a first recess in the fin having a first width and a first depth and forming a second recess in the first recess having a second width that is less than the first width and having a second depth that is greater than the first depth. The method may further include forming a source/drain region in the first and second recesses.

Integrated circuit devices including finFETs and methods of forming the same

A method of forming a semiconductor device is provided, comprising forming a plurality of hard masks on a substrate by patterning an insulating layer; forming a plurality of trenches in the substrate, each trench having trench walls disposed between two adjacent masks and extending vertically from a bottom portion to an upper portion; forming an insulating layer on the hard masks and the trench walls; forming a conductive layer on the insulating layer; etching the conductive layer to form conductive layer patterns to fill the bottom portions of the trenches; depositing a buffer layer on the conductive layer patterns and the trench walls; and filling the upper portions of the trenches with a capping layer.

Recess gate transistor

In a method of manufacturing a semiconductor device, a recess is formed in an active region of a substrate. A gate insulation layer is formed in the first recess. A barrier layer is formed on the gate insulation layer. A preliminary nucleation layer having a first resistance is formed on the barrier layer. The preliminary nucleation layer is converted into a nucleation layer having a second resistance substantially smaller than the first resistance. A conductive layer is formed on the nucleation layer. The conductive layer, the nucleation layer, the barrier layer and the gate insulation layer are partially etched to form a buried gate structure including a gate insulation layer pattern, a barrier layer pattern, a nucleation layer pattern and a conductive layer pattern.

Methods of manufacturing semiconductor devices having low resistance buried gate structures

A recess gate of a semiconductor device is provided, comprising: a substrate having a recess formed therein; a metal layer formed at the bottom of the recess; a polysilicon layer formed over the metal layer; and a source region and a drain region formed adjacent to the polysilicon layer and spaced from the metal layer. A method of forming a semiconductor device is also provided, comprising forming a substrate and a source and drain layer; forming a recess and depositing a gate insulation layer therein; forming a first conductive layer on the gate insulation layer; forming a first conductive layer pattern by recessing the first conductive layer; forming a second conductive layer on the first conductive layer pattern; forming a second conductive layer pattern by patterning the second conductive layer to overlap the source and drain layer; depositing an insulating layer on the second conductive layer pattern and the source and drain layer; and planarizing the insulating layer to form a cap on the second conductive layer pattern.

Provided are a semiconductor device having a buried word line structure in which a gate electrode and a word line may be buried within a substrate to reduce the height of the semiconductor device and to reduce the degradation of the oxide layer caused by chlorine ions from the application of a TiN metal gate, and a method of fabricating the semiconductor device. The semiconductor device may comprise a semiconductor substrate defined by a device isolation layer and comprising an active region including a trench and one or more recess channels, a gate isolation layer on the surface of the trench, a gate electrode layer on the surface of the gate isolation layer, and a word line by which the trench may be buried on the surface of the gate electrode layer.

Semiconductor having buried word line cell structure and method of fabricating the same

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Suwon-si, South Korea

Si-Hyung Lee