International Business Machines Corporation

Globalfoundries Inc.

Stmicroelectronics Gmbh

Freudenberg Nonwovens

Shyng-Tsong Chen

Chih-Chao Yang

Terry Allen Spooner

Shom Ponoth

Kenneth M Davis

Kenneth Parker Rodbell

Oscar Kai Chi Hsu

Takashi Ando

David V Horak

Takeshi Nogami

Timothy Joseph Dalton

Qinghuang Lin

Griselda Bonilla

Kaushik Arun Kumar

Kelly Malone

Wei-Tsu Tseng

Jean Vangsness

Koichi Motoyama

David Lee Rath

Mahadevaiyer Krishnan

Lawrence Alfred Clevenger

Steven J Holmes

Sampath Purushothaman

Matthew Earl Colburn

Hiroyuki Miyazoe

Yunpeng Yin

Chandrasekhar Narayan

Yongan Xu

Michael F Lofaro

Iqbal Rashid Saraf

Daniel C Edelstein

Charles W Koburger, Iii

Son Van Nguyen

Michael Rizzolo

Hariklia Deligianni

Christopher J Penny

Katherine Lynn Saenger

Sanjay C Mehta

Wai-Kin Li

Yann Mignot

Sandra Guy Malhotra

Andrew Herbert Simon

John Michael Cotte

Hosadurga K Shobha

Chi-Chun Liu

John Anthony Fitzsimmons

Satyanarayana Venkata Nitta

Dongbing Shao

Cheng Chi

Stephen Edward Greco

Kaushik Chanda

Panayotis Constantinou Andricacos

Samuel S Choi

Chao-Kun Hu

Wenhui Wang

Judith Marie Rubino

Fen Fen Jamin

Steffen K Kaldor

Sylvie M Mignot

Sean P E Smith

Scott Clayton Billings

David S Gilbride

Alex Siu Keung Chung

Shawn M Walsh

Theodorus E Standaert

Zheng Xu

Soon-Cheon Seo

Baozhen Li

Oscar Van Der Straten

Stephen McConnell Gates

Elbert Emin Huang

Roy Rongqing Yu

Ashim Dutta

Muthumanickam Sankarapandian

Jeffrey Curtis Hedrick

Dexin Kong

Michael D Armacost

Michael Wayne Lane

Christy Sensenich Tyberg

Youngseok Kim

Hao Tang

Ryan O Jung

Anita Madan

Jing Sha

Steven E Molis

Stefanie Ruth Chiras

Philippe M Vereecken

Ronald Anthony DellaGuardia

Minakshisundaran Balasubramanian Anand

Nancy R Klymko

Philippe Mark Vereecken

Simon M Karecki

Neal V Lafferty

Woody Ray Smith

Heidi Lee Baks

Nicholas Colvin Masi Fuller

Robert Rosenburg

Embodiments of the invention include a method for fabricating a semiconductor device and the resulting structure. A substrate having an embedded memory area interconnect structure and an embedded non-memory area interconnect structure is provided, the memory area interconnect structure comprising metal interconnects formed in dielectric material. A dielectric cap layer is formed on exposed surfaces of the memory area and the non-memory area. A bottom metal contact is formed on a first metal interconnect of the memory area interconnect structure, the bottom metal contact in a trench in the dielectric cap layer. A memory element stack pillar is formed on the bottom metal contact. A dielectric layer is formed on exposed surfaces of the memory area and the non-memory area utilizing a non-conformal deposition process. The dielectric layer is removed from sidewalls of the memory element stack pillar.

Magnetoresistive random-access memory (MRAM) with preserved underlying dielectric layer

Back end of line metallization structures and methods for fabricating self-aligned vias. The structures generally include a first interconnect structure disposed above a substrate. The first interconnect structure includes a metal line formed in a first interlayer dielectric. A second interconnect structure overlies the first interconnect structure. The second interconnect structure includes a second cap layer on the first interlayer dielectric, a second interlayer dielectric thereon, and at least one self-aligned via in the second interlayer dielectric conductively coupled to at least a portion of the metal line of the first interconnect structure, wherein any misalignment of the at least one self-aligned via results in the at least one self-aligned via landing on both the metal line of the first interconnect structure and the second cap layer. The second cap layer is an insulating material.

Interconnect structures including self aligned vias

A method is presented for forming self-aligned vias by employing a top level line pattern. The method includes forming first conductive lines within a first dielectric material, recessing one conductive line of the conductive lines to define a first opening, filling the first opening with a second dielectric material, and forming a sacrificial block perpendicular to and in direct contact with a non-recessed first conductive line. The method further includes forming a single via directly underneath the sacrificial block by recessing the non-recessed first conductive line, removing the sacrificial block to define a second opening, and filling the second opening with a conductive material to define a second conductive line such that the single via aligns to both the non-recessed first conductive line and the second conductive line.

Interconnect integration scheme with fully self-aligned vias

A method is presented for forming self-aligned vias by employing top level line double patterns. The method includes forming a plurality of first conductive lines within a first dielectric material, recessing one or more of the plurality of first conductive lines to define first openings, filling the first openings with a second dielectric material, and forming sacrificial blocks perpendicular to the plurality of first conductive lines. The method further includes forming vias directly underneath the sacrificial blocks, removing the sacrificial blocks, and constructing a plurality of second conductive lines such that the vias align to both the plurality of first conductive lines and the plurality of second conductive lines.

Double patterning interconnect integration scheme with SAV

Embedded BEOL memory devices having a top electrode pillar are provided. In one aspect, a method of forming an embedded memory device includes: depositing a first ILD on a substrate; forming first/second interconnect in the first ILD over logic/memory regions of the substrate; depositing a capping layer onto the first ILD; forming a memory film stack on the capping layer; patterning the memory film stack into a memory device(s) including a bottom electrode, a dielectric element, and a top electrode; patterning the top electrode to form a pillar-shaped top electrode; depositing a conformal encapsulation layer over the capping layer and memory device(s); depositing a second ILD over the conformal encapsulation layer; and forming a first metal line(s) in the second ILD in contact with the first interconnect(s), and a second metal line(s) in the second ILD in contact with the pillar-shaped top electrode. A device is also provided.

Embedded BEOL memory device with top electrode pillar

In accordance with an embodiment of the present invention, a photolithographic mask is provided. The photolithographic mask includes at least one merged via pattern in the photolithographic mask for printing a merged via opening in a resist layer, wherein the at least one merged via pattern includes a compound shape having a first rectangular opening portion and a second rectangular opening portion that intersect at an angle.

Tight pitch via structures enabled by orthogonal and non-orthogonal merged vias

A method is presented for protecting resistive random access memory (RRAM) stacks within a resistive memory crossbar array. The method includes forming conductive lines within an interlayer dielectric (ILD), forming a metal nitride layer over at least one conductive line, forming a bottom electrode, forming a RRAM stack over the metal nitride layer, the RRAM stack including a first top electrode and a second top electrode, undercutting the second top electrode to define recesses, and filling the recesses with inner spacers.

Resistive memory crossbar array with top electrode inner spacers

Methods and systems for performing an electronic design. A layout of a via of an electronic design is obtained and a determination is made if the layout of the via satisfies one or more retargeting conditions, at least one of the retargeting conditions being that a first edge of a metal line is within a specified distance from a first edge of the via and a second edge of the metal line is within the specified distance from a second edge of the via, the first edge of the metal line being parallel to the first edge of the via and the second edge of the metal line being parallel to the second edge of the via; and reducing a resistance of the via by the layout of the via is retargeted in response to the retargeting conditions being satisfied.

Via design optimization to improve via resistance

Back end of line (BEOL) structures and methods generally includes forming at least two adjacent conductors separated by a space formed in a first dielectric material, wherein a liner layer is intermediate the first dielectric material and each of the at least two adjacent conductors. A second dielectric material in the space between the at least two adjacent conductors and in contact with the first dielectric material at a bottom surface thereof, wherein the first dielectric material is different from the second dielectric material, and wherein the first dielectric material has a nitrogen enriched surface at an interface between the first dielectric material and the second dielectric material. The nitrogen enriched surface can be formed by plasma nitridation, thermal nitridation, or laser annealing in the presence of nitrogen gas, ammonia, or a combination thereof.

Surface modified dielectric refill structure

A method is presented for protecting resistive random access memory (RRAM) stacks within a resistive memory crossbar array. The method includes forming a plurality of conductive lines within an interlayer dielectric (ILD), forming a RRAM stack including a bottom electrode, a top electrode, and a bi-layer hardmask, forming a low-k dielectric layer over the RRAM stack, removing a first layer of the bi-layer hardmask during a via opening, and removing a second layer of the bilayer hardmask concurrently with a plurality of sacrificial layers formed over the low-k dielectric layer.

Resistive memory crossbar array compatible with Cu metallization

A method of forming a via to an underlying layer of a semiconductor device is provided. The method may include forming a pillar over the underlying layer using a sidewall image transfer process. A dielectric layer is formed over the pillar and the underlying layer; and a via mask patterned over the dielectric layer, the via mask having a mask opening at least partially overlapping the pillar. A via opening is etched in the dielectric layer using the via mask, the mask opening defining a first lateral dimension of the via opening in a first direction and the pillar defining a second lateral dimension of the via opening in a second direction different than the first direction. The via opening is filled with a conductor to form the via. A semiconductor device and via structure are also provided.

Via formation using sidewall image transfer process to define lateral dimension

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Patterson, NY, United States of America

Shyng-Tsong Chen