Silicon Integrated Systems Corporation

Industrial Technology Research Institute

Shyh-Dar Lee

Chen-Chiu Hsue

Chung-I Chang

Jen-Hann Tsai

Lai-Juh Chen

Hung-Wen Chiou

Chien-Mei Wang

Chun-Feng Nien

Shuo-Yen Chou

A dual damascene process is provided on a semiconductor substrate, having a conductive structure and a low-k dielectric layer covering the conductive structure. A first hard mask and a second hard mask are sequentially formed on the low-k dielectric layer, in which at least the hard mask contacting the low-k dielectric layer is of metallic material. Next, a first opening is formed in the second hard mask over the conductive structure, and a second opening is then formed in the first hard mask under the first opening. Afterward, the low-k dielectric layer that is not covered by the first hard mask is removed, thus a via hole is formed. Thereafter, the first hard mask that is not covered by the second hard mask is removed, and then the exposed low-k dielectric layer is removed. Thereby, a trench is formed over the via hole.

Dual damascene process using metal hard mask

A method for improving adhesion of a low k dielectric to a barrier layer. A substrate covered by an insulating layer having copper interconnects is provided. A sealing layer is formed on the copper interconnects and the insulating layer. A plasma treatment is performed on the sealing layer by a reaction gas including at least one of CO , NH , NO , SiH , trimethylsilane, and tetramethylsilane. A low k dielectric layer is formed on the sealing layer.

Method for improving adhesion of a low k dielectric to a barrier layer

A capacitor in which the lower electrode and an interconnect line are located at the same level. The capacitor includes a first conductive line and a second conductive line on a substrate located at the same level, wherein the second conductive line defines a capacitor region and is used as a lower electrode of the capacitor; an insulating layer on the substrate, the first conductive line, and the second conductive line; and a third conductive line on the insulating layer in the capacitor region such that the third conductive line is used as an upper electrode of the capacitor. Since the lower electrode and an interconnect line can be in-situ (concurrently) formed to be located at the same level, one mask can be omitted compared with the conventional method, and production costs can be reduced.

Capacitor with lower electrode located at the same level as an interconnect line

A method of forming a stacked dielectric layer on a semiconductor substrate having metal patterns. A first dielectric layer is formed on the semiconductor substrate. Next, a second dielectric layer is formed on the first dielectric layer to generate a composite dielectric layer. The second dielectric layer has a dielectric constant (k) higher than that of the first dielectric layer, a hardness higher than that of the first dielectric layer, and a thickness less than that of the first dielectric layer. The steps of forming the first dielectric layer and second dielectric layer can be repeated at least 2 to 3 times to form a stacked dielectric layer.

Method of forming a stacked dielectric layer on a semiconductor substrate having metal patterns

A method of reducing micro-scratches during tungsten CMP. Tungsten CMP with a standard tungsten slurry is first provided on the exposed surfaces of a tungsten plug and a IMD layer on a semiconductor substrate. The tungsten CMP with an oxide slurry is then provided on the polished surfaces of the tungsten plugs and the IMD layer.

Method of reducing micro-scratches during tungsten CMP

Disclosed is a method for forming selective protection layers on copper interconnects in a damascene process. A copper layer is deposited overlying a dielectric layer and filling interconnect trenches which are previously formed in the dielectric layer. The excess copper layer is polished by a chemical mechanical polishing process with a slurry comprising an aluminum organic substance. The aluminum organic substance reacts with copper via annealing to selectively form aluminum-copper alloys on the copper interconnects. The aluminum-copper alloys are then oxidized to form aluminum oxide protection layers capping the copper interconnects.

Method for forming selective protection layers on copper interconnects

A method for fabricating a polysilicon capacitor. The method includes the following steps. A polysilicon layer is formed on a substrate. The polysilicon layer is patterned to concurrently form a first polysilicon line and a second polysilicon line. The second polysilicon line defines a polysilicon capacitor region and is used as a lower electrode of the polysilicon capacitor. Next, an insulating layer is formed conformably on the substrate, the first polysilicon line, and the second polysilicon line. A first dielectric layer is formed on the insulating layer, which is then subjected to planarization treatment such that the planarization treatment ends up to the insulating layer. Finally, a third polysilicon line is formed on the insulating layer in the polysilicon capacitor region such that the third polysilicon line is used as an upper electrode of the polysilicon capacitor. Since the lower electrode and the interconnect line can be in-situ (concurrently) formed, one mask can be omitted compared with the conventional method, and production costs can be reduced.

Method for fabricating polysilicon capacitor

A metal capacitor in damascene structures is provided. A first Cu wire and a second Cu wire are located in a first insulator. A first sealing layer is located on the first and the second Cu wires. A second insulator is located on the first sealing layer. A third insulator is located on the second insulator, and acting as an etch stop layer. A first Cu plug and a second Cu plug are located in the first sealing layer, the second insulator and the third insulator. A capacitor is located on the third insulator and the first Cu plug, the capacitor having an upper electrode, a capacitor dielectric and a bottom electrode with the same pattern each other, wherein the bottom electrode is connected to the first Cu wire through the first Cu plug. A conducting wire is located on the third insulator and the second Cu plug, wherein the conducting wire is connected to the second Cu wire through the second Cu plug. A fourth insulator is located on the conducting wire. A fifth insulator with a flat surface is located on the upper electrode, the fourth insulator and the third insulator. A plurality of dual damascene structures including a third plug, a fourth Cu plug, a third Cu wire and a fourth Cu wire are located in the fifth insulator, wherein an upper electrode of the capacitor is connected to the third Cu wire through the third Cu plug, and the conducting wire is connected to the fourth Cu wire through the fourth Cu plug. A second sealing layer is located on the third and fourth Cu wires.

Metal capacitor in damascene structures

This invention provides a metal capacitor with damascene structures. Before the thin-film capacitor is formed, the underlying interconnections, such as a first Cu wire and a second Cu wire, are fabricated with Cu by damascene processes. The thin-film capacitor is composed of a first metal layer contacting the first Cu wire, a dielectric layer and a second metal layer. A first Cu damascene structure and a second Cu damascene structure are disposed on the thin-film capacitor and the second Cu wire, respectively.

Metal capacitors with damascene structures

An organic copper diffusion barrier layer having low dielectric constant is provided. The organic copper diffusion barrier layer can be applied to a dual damascene structure, which is formed between a copper wiring layer and an organic dielectric layer, to defend copper diffusion from the copper wiring layer into the organic dielectric layer. The organic copper diffusion barrier layer includes a benzocyclo polymer, which it has a benzene ring functional group that can catch copper and prevent copper diffusing into the organic dielectric layer. The problem of thermal diffusion and electro-migration can be avoided.

Method of making an organic copper diffusion barrier layer

A process for fabricating a dual damascene structure. First, a substrate having a dielectric layer is provided. A cap layer and a mask layer with at least one trench pattern are sequentially formed on the dielectric layer. Thereafter, a photoresist layer with at least one via pattern aligned with the trench pattern is formed overlaying the mask layer and part of the cap layer. Next, the via pattern is transferred into the cap layer and the upper half of the dielectric layer. The photoresist layer is then removed. Subsequently, the trench pattern is transferred into the cap layer and the upper half of the dielectric layer, and simultaneously the via pattern in the upper half of the dielectric layer is transferred into the lower half of the dielectric layer. Finally, the trench and the via in the dielectric layer are filled with a conductive layer.

Dual damascene process

This invention provides a metal capacitor with damascene structures. Before the thin-film capacitor is formed, the underlying interconnections, such as a first Cu wire and a second Cu wire, are fabricated with Cu by damascene processes. The thin-film capacitor composed of a first metal layer contacting the first Cu wire, a dielectric layer and a second metal layer is formed in an insulator and a stop layer. A first Cu damascene structure and a second Cu damascene structure are disposed on the thin-film capacitor and the second Cu wire, respectively.

Metal capacitors with damascene structures and method for forming the same

This invention provides a method for forming a metal capacitor in a damascene process. Before the thin-film capacitor is formed, the underlying interconnections are fabricated with Cu metal by damascene process. The lower electrode is formed in a dual damascene process, which is also used to form the dual damascene structures comprising wires and plugs. An insulator is disposed to isolate the dual damascene structures with each other. In this dual damascene process, an anti-reflection layer is used and formed on the insulator, and the anti-reflection layer is also used as a hard mask layer, a polishing stop layer and an etching stop layer. Then, another insulator and a metal layer are formed on the anti-reflection layer, and encounter a photolithography step and an etching step to obtain an upper electrode and a capacitor insulator. After forming the metal capacitor, the upper interconnections are fabricated with another dual damascene processes.

Method for forming a metal capacitor in a damascene process

A dual damascene process is applied on a semiconductor substrate having a dual damascene opening with a via hole which exposes a metal wire and is surrounded by a first low-k dielectric layer, and a trench which is over the via hole and surrounded by a second low-k dielectric layer. An in-situ oxide liner, serving as a dielectric barrier layer, is formed on the sidewall of the first low-k dielectric layer and the second low-k dielectric layer. A metal barrier layer is conformally deposited on the exposed surface of the semiconductor substrate to cover the sidewall and bottom of the dual damascene opening. The dual damascene opening is filled with a conductive layer, and then the excess conductive layer outside the trench level is polished away by a CMP process.

Dual damascene process using an oxide liner for a dielectric barrier layer

This invention provides a dual damascene structure having capacitors. Before the thin-film capacitor is formed, the underlie interconnections are fabricated with Cu metal by damascene processes. The capacitor is formed by depositing a first metal layer, an insulator and a second metal layer. Then, the stacked layers are subjected to two masking and etching processes to form the thin-film capacitor and the metal wire. After forming the capacitor, the upper interconnections are fabricated with Cu metal by damascene processes.

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Hsinchu Hsien, Taiwan

Shyh-Dar Lee