Globalfoundries Inc.

Shyam Pal

Andy C Wei

Guillaume Bouche

Jinping Liu

Huang Liu

Haigou Huang

Roderick Alan Augur

Jason Eugene Stephens

Xiang Hu

Huy Cao

Xintuo Dai

Bharat V Krishnan

Linus Jang

Craig Child

Akshey Sehgal

Mark Alexander Zaleski

Matthew Thomas Herrick

Norman Chen

Haifeng Sheng

Chang Ho Maeng

Yuyang Sun

Sohan Singh Mehta

Kenneth Andrew Bates

David Michael Permana

Jeong Soo Kim

Anbu Selvam K M Mahalingam

Anthony Ozzello

Ja-Hyung Han

SangWoo Lim

Granger Lobb

Aleksandra Clancy

Semiconductor devices and methods of fabricating the semiconductor devices with chamfer-less via multi-patterning are disclosed. One method includes, for instance: obtaining an intermediate semiconductor device; performing a trench etch into a portion of the intermediate semiconductor device to form a trench pattern; depositing an etching stack; performing at least one via patterning process; and forming at least one via opening into a portion of the intermediate semiconductor device. An intermediate semiconductor device is also disclosed.

Devices with chamfer-less vias multi-patterning and methods for forming chamfer-less vias

Methods of MOL S/D contact patterning of RMG devices without gouging of the Rx area or replacement of the dielectric are provided. Embodiments include forming a SOG layer around a RMG structure, the RMG structure having a contact etch stop layer and a gate cap layer; forming a lithography stack over the SOG and gate cap layers; patterning first and second TS openings through the lithography stack down to the SOG layer; removing a portion of the SOG layer through the first and second TS openings, the removing selective to the contact etch stop layer; converting the SOG layer to a SiOlayer; forming a metal layer over the SiOlayer; and planarizing the metal and SiOlayers down to the gate cap layer.

Siloxane and organic-based MOL contact patterning

A method includes forming a stack of hard mask layers above a process layer. The stack includes first, second and third hard mask layers. The third hard mask layer is patterned to define therein a first mask element and to expose portions of the second hard mask layer. The second hard mask layer is patterned to define therein a second mask element below the first mask element and a third mask element, and to expose portions of the first hard mask layer. The first hard mask layer is patterned to define therein a fourth mask element below the second mask element, a fifth mask element below the third mask element, and a sixth mask element, and to expose portions of the process layer. The process layer is etched to remove portions of the process layer not covered by the first hard mask layer.

Multiple patterning process for forming pillar mask elements

Methods are provided for fabricating semiconductor integrated circuits including isolated trench features. In one embodiment, a method includes providing a semiconductor substrate with an overlying process layer. A trench pattern to be etched into the process layer is determined and that trench pattern is decomposed into first and second patterns, the second pattern including an isolated trench. First and second lithographic masks are formed to implement the first and second patterns, the second mask implementing the second pattern, the isolated trench, and a plurality of density balancer patterns symmetrically positioned with respect to the isolated trench. A first resist layer is patterned with the first lithographic mask and the process layer is etched with the first resist layer. A second resist layer is patterned with the second lithographic mask and the process layer is etched with the second resist layer to implement the required trench pattern in the process layer.

Method for fabricating a semiconductor integrated circuit with a litho-etch, litho-etch process for etching trenches

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Clifton Park, NY, United States of America

Shyam Pal