Taiwan Semiconductor Manufacturing Comp. Ltd.

Shwangming Jeng

Syun-Ming Jang Jang

Chen-Hua Douglas Yu

Chung-Long Chang

Lain-Jong Li

Shau-Lin Shue

Chung-Te Lin

Kong-Beng Thei

Mei-Yun Wang

Bao-Ru Young

Jeng-Horng Chen

Weng Chang

Ying-Ho Chen

Chu-Yun Fu

Li-Chih Chao

Chen-Fang Chung

Yuan-Horng Chiu

Chi-Shiung Tsai

Low k dielectrics such as black diamond have a tendency to delaminate from the edges of a silicon wafer, causing multiple problems, including blinding of the alignment mark. This problem has been overcome by inserting a layer of silicon nitride between the low k layer and the substrate. A key requirement is that said layer of silicon nitride be under substantial compressive stress (at least 5&times;10 dynes/cm ). In the case of a layer of black diamond, on which material the invention is particularly focused, a nucleating layer is also inserted between the silicon nitride and the black diamond. A process for laying down the required layers is described together with an example of applying the invention to a dual damascene structure.

Solution to black diamond film delamination problem

A method of cleaning a low-k material etched opening, comprising the following steps. A semiconductor structure having an exposed device therein is provided. An etch stop layer is formed over the semiconductor structure and the exposed device. A layer of low-k material is formed over the etch stop layer semiconductor structure and device. A patterned layer of photoresist is formed over the low-k material layer. The patterned photoresist layer is used as a mask to etch low-k material layer is etched to form an opening exposing at least a portion of the etch stop layer over the device. The patterned photoresist layer is removed by a low temperature ashing process at a temperature from about 23 to 27&deg; C., and more preferably about 25&deg; C. (room temperature). The exposed portion of the etch stop layer over the device is removed to expose the underlying device by a low pressure, low bias etching process at a pressure from about 8 to 12 milli-Torr and a bias power from about 25 to 35 W. The exposed underlying device and the opening are cleaned by removing any remaining low pressure, low bias etch polymer and etch residue by a fully dry-type cleaning process using an H He gas.

Method of cleaning a copper/porous low-k dual damascene etch

A method for making reliable low-resistance contacts between closely spaced FET gate electrodes having high-aspect-ratio spacings. Polysilicon gate electrodes are formed. A conformal insulating layer is deposited and anisotropically etched back to form sidewall spacers on the gate electrodes. During conventional etch-back, the etch rate of the insulating layer between the closely spaced gate electrodes is slower resulting in a residual oxide that prevents the formation of reliable low-resistance contacts. This residual oxide requires an overetch in a hydrofluoric acid solution prior to forming silicide contacts. The wet overetch results in device degradation. A nitrogen or germanium implant is used to amorphize the oxide and to increase the wet etch rate of the residual oxide. Using this amorphization the wet etch that is commonly used as a pre-clean prior to forming silicide contacts can be used to remove the residual silicon oxide without overetching. The implant also results in a smoother interface between the silicide and the silicon substrate, which results in lower sheet resistance.

Method for making low-resistance silicide contacts between closely spaced electrically conducting lines for field effect transistors

A new configuration of a basic concatenatable integrated modular multiple chamber vacuum processing system for wafer manufacturing vacuum processes is disclosed. The basic system includes at least one multiple ported transfer vacuum chamber, an R-&thgr; transfer means contained within each chamber, a multiplicity of ports adaptable for appending a variety of vacuum process chambers as well as forming entrance/exit ports with at least one dual port pass through chamber attached to one entrance/exit port. Each pass through chamber contains a wafer alignment and/or orientation means for aligning or orienting the wafer as necessary in any of the appended process chambers. The configuration minimizes alignment or orientation errors due to inherent instability of the concatenated transfer means operations.

Multiple chamber vacuum processing system configuration for improving the stability of mark shielding process

A method of using a monitor wafer to monitor the shielding of alignment marks during material deposition steps. The alignment marks are shielded using shielding tabs attached to the clamp ring used to clamp the wafer during deposition of a layer of material. An oxide monitor wafer, having the same size and shape of product wafers, has monitor marks formed thereon. The center of the monitor marks has the same location on the monitor wafer as the alignment marks have on the product wafers. The monitor wafer is subjected to the same processing steps as the product wafers through the step of material deposition. The clamp ring is removed from the monitor wafer and the distance from the center of the monitor marks and the edge of the deposited material is determined. The monitor marks are formed so that the distance from the center of the monitor marks and the edge of the deposited material can be determined by direct observation of the monitor marks. The monitor wafers are processed after adjustments to or maintenance on equipment or after a fixed number of product wafers are processed.

Method for monitoring alignment mark shielding

A method for forming a dual damascene conductor interconnection layer within an inter-level metal dielectric (IMD) layer formed upon a substrate employed within a microelectronics fabrication. There is provided a substrate employed within a microelectronics fabrication. There is then formed over the substrate a series of conductor lines. There is then formed over the substrate a dielectric layer. There is then formed over the dielectric layer an intermediate second dielectric layer. There is then formed over the substrate a patterned photoresist etch mask layer. There is then etched the pattern of the photoresist etch mask-layer into and through the dielectric layers, followed by stripping the photoresist layer. There is then treated the exposed dielectric layer surface to a reactive gas to form a reacted surface layer. There may then be formed over the substrate additional patterned photoresist etch mask layers, with attenuated degradation of the dielectric layers due to the organic materials and methods for cleaning and stripping same.

Method of protecting a low-K dielectric material

Low dielectric inter-metal dielectric (IMD) layers made of hydrogen silsesquioxane (HSQ) or methyl silsesquioxane (MSQ) spin-on-glass do not have good thermal conductivity as compared to regular oxides, in addition the adhesion of HSQ or MSQ is worse than that of oxide to oxide layers Methods are disclosed and illustrated to improve the heat transfer by providing metal dummy plugs under and/or around bonding pads or between metallization layers. The arrangement and numbers of dummy plugs depends on the heat to be transferred and varies with the application. Good thermal conductivity is of particular importance because the effects of high local temperature around bonding pads during chip bonding results in thermal stress and delamination of the IMD layers. The use of bonding pads provides other benefits as well.

Process for low-k dielectric with dummy plugs

A method for forming a metal silicide layer. There is first provided a substrate. There is then formed over the substrate a silicon layer, where the silicon layer has other than an amorphous silicon surface. There is then annealed thermally the silicon layer at a temperature greater than a silicidation temperature for forming a metal silicide layer upon the silicon layer to thus form from the silicon layer a thermally annealed silicon layer. Finally, there is then deposited upon the thermally annealed silicon layer a metal silicide forming metal while employing a metal deposition method such that upon contact with the thermally annealed silicon layer the metal silicide forming metal reacts in-situ to form a metal silicide layer upon a partially consumed thermally annealed silicon layer formed from the thermally annealed silicon layer.

Thermal annealing method for forming metal silicide layer

A method for forming a microelectronic layer within a microelectronic fabrication first employs a substrate. There is then formed over the substrate a target microelectronic layer. There is then formed upon the target microelectronic layer a sacrificial smoothing layer. Finally, there is then etched the sacrificial smoothing layer completely from the target microelectronic layer while partially etching the target microelectronic layer to form a partially etched target microelectronic layer with an enhanced surface smoothness in comparison with the target microelectronic layer.

Etchback method for forming microelectronic layer with enhanced surface smoothness

There is provided a method for smoothing the surface of undoped polysilicon regions of a CMOS structure, primarily gate regions. A direct HPD-CVD argon sputter is used improve the surface roughness by a factor of more than 50%. The argon plasma sputter may be used either alone or in conjunction with a thin capping layer of oxide, nitride or oxynitride. The devices manufactured using the process exhibit excellent electrical characteristics and improved reliability compared to devices made using conventional manufacturing processes.

Method for smoothing polysilicon gate structures in CMOS devices

A method for forming within a microelectronics fabrication a dielectric layer formed over, around and between patterned conductor layers. There is first provided a substrate employed within a microelectronics fabrication upon which is formed a patterned conductor layers. There is then formed over the patterned conductor layer a silicon oxide dielectric layer. There is then treated the silicon oxide dielectric layer to an anisotropic sputter etching process to remove silicon oxide dielectric material without re-deposition from the bottom of the gap between lines of the patterned conductor layer and to reform the silicon oxide dielectric layers on the sidewalls of the patterned lines to form spacer layers thereon. Both the silicon oxide dielectric layer deposition process and the sputter etching process may be repeated as desired to form the desired depth of trench and shape of spacer layer. There is then exposed the substrate to a nitrogen plasma. There is then formed over the substrate a gap filling silicon oxide dielectric layer to complete the formation of the inter-level dielectric layer with minimal void content in gaps between patterned lines.

Method for forming gap filling silicon oxide intermetal dielectric (IMD)

A method is described for removing residual metal, such as tungsten, from the edge region of a wafer. After tungsten is deposited on a wafer to fill via holes in a dielectric the wafer is planarized using Chemical Mechanical Polishing, CMP. The CMP does not remove the tungsten from the edge of the wafer. After conductor metals for a layer of conducting electrodes has been deposited a layer of photoresist is formed on the wafer and patterned to clear the metals from over the alignment marks. This photoresist is then removed from the edge region of the wafer. The residual metals are then etched away from the edge region of the wafer using the remaining photoresist as a mask during the same etching step used to remove metals from the alignment marks or during a separate etching step. In one embodiment the alignment marks and laser marks are relocated to the edge region of the wafer and the residual metals are etched away from the edge region of the wafer during the same etching step used to remove metals from the alignment marks and laser marks.

Method of removing tungsten near the wafer edge after CMP

A method to reduce to reduce DRAM capacitor STI junction leakage current. A Shallow Trench Isolation opening is formed, within this opening Field Oxide is deposited. The top surface of the FOX is etched down and a second layer of oxide is deposited over the FOX and the adjacent active regions. This second layer of oxide is etched bringing the top surface down to below the level of the top surface of the surrounding active areas but leaving spacers where the top surface of the FOX intersects with the active areas.

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Hsin-Chu, Taiwan

Shwangming Jeng