Taiwan Semiconductor Manufacturing Comp. Ltd.

Shwang-Ming Jeng

Keng-Chu Lin

Chung-Chi Ko

Chen-Hua Douglas Yu

Tien-I Bao

Chia-Cheng Chou

Chin-Hsiang Lin

Teng-Chun Tsai

Joung-Wei Liou

Yung-Cheng Lu

Lain-Jong Li

Shing-Chyang Pan

Tsu-Hsiu Perng

Fu-Ting Yen

Syun-Ming Jang Jang

Chih-Lung Lin

Mei-Ling Chen

Ting-Yu Shen

Kuan-Chen Wang

Wen-Chih Chiou

Chi-Ming Yang

Po-Cheng Shih

Zhen-Cheng Wu

Chia Cheng Chou

Han-Hsin Kuo

Jun-Lung Huang

Huilin Chang

Fang-Wen Tsai

Yichi Liao

Jeng-Cheng Liu

Yee-Chia Yeo

Pei-Ren Jeng

Liang-Guang Chen

Shen-Nan Lee

Shich-Chang Suen

Hsin-Yi Tsai

Fang Wen Tsai

Han-Ti Hsiaw

He Hui Peng

Soon-Kang Huang

Hui-Chun Yang

Shih-Ming Wang

Huang Soon Kang

Chia-Chiung Lo

Ming Ling Yeh

I-i Chen

Fu-Chi Hsu

Grace H Ho

Wne-Pin Peng

Kin-Weng Wang

Syan-Mang Jang

An embodiment method includes depositing a first dielectric film over and along sidewalls of a semiconductor fin, the semiconductor fin extending upwards from a semiconductor substrate. The method further includes depositing a dielectric material over the first dielectric film; recessing the first dielectric film below a top surface of the semiconductor fin to define a dummy fin, the dummy fin comprising an upper portion of the dielectric material; and forming a gate stack over and along sidewalls of the semiconductor fin and the dummy fin.

Dummy fin structures and methods of forming same

A method includes forming a metal hard mask over a low-k dielectric layer. The step of forming the metal hard mask includes depositing a sub-layer of the metal hard mask, and performing a plasma treatment on the sub-layer of the metal hard mask. The metal hard mask is patterned to form an opening. The low-k dielectric layer is etched to form a trench, wherein the step of etching is performed using the metal hard mask as an etching mask.

Forming interconnect structure using plasma treated metal hard mask

A polisher includes a wafer carrier, a polishing head, a movement mechanism, and a rotation mechanism. The wafer carrier has a supporting surface. The supporting surface is configured to carry a wafer thereon. The polishing head is present above the wafer carrier. The polishing head has a polishing surface. The polishing surface of the polishing head is smaller than the supporting surface of the wafer carrier. The movement mechanism is configured to move the polishing head relative to the wafer carrier. The rotation mechanism is configured to rotate the polishing head relative to the wafer carrier.

Polisher, polishing tool, and polishing method

A method includes etching a low-k dielectric layer on a wafer to form an opening in the low-k dielectric layer. An amount of a detrimental substance in the wafer is measured to obtain a measurement result. Process conditions for baking the wafer are determined in response to the measurement result. The wafer is baked using the determined process conditions.

Automatically adjusting baking process for low-k dielectric material

The present disclosure provides a method of fabricating a semiconductor device, a semiconductor device fabricated by such a method, and a chemical mechanical polishing (CMP) tool for performing such a method. In one embodiment, a method of fabricating a semiconductor device includes providing an integrated circuit (IC) wafer including a metal conductor in a trench of a dielectric layer over a substrate, and performing a chemical mechanical polishing (CMP) process to planarize the metal conductor and the dielectric layer. The method further includes cleaning the planarized metal conductor and dielectric layer to remove residue from the CMP process, rinsing the cleaned metal conductor and dielectric layer with an alcohol, and drying the rinsed metal conductor and dielectric layer in an inert gas environment.

Metal conductor chemical mechanical polish

A method for forming an integrated circuit includes forming a low-k dielectric layer over a semiconductor substrate, etching the low-k dielectric layer to form an opening, forming a dielectric barrier layer covering at least sidewalls of the opening, performing a treatment to improve a wetting ability of the dielectric barrier layer, and filling the opening with a conductive material, wherein the conductive material is in contact with the dielectric barrier layer.

Low-k interconnect structures with reduced RC delay

An Active Energy Assist (AEA) baking chamber includes an AEA light source assembly and a heater pedestal. The AEA baking chamber further includes a controller for controlling a power input to the AEA light source assembly and a power input to the heater pedestal. A method of forming interconnects on a substrate includes etching a substrate and wet cleaning the etched substrate. The method further includes active energy assist (AEA) baking the substrate after the wet-cleaning. The AEA baking includes placing the substrate on a heater pedestal in an AEA chamber, exposing the substrate to light having a wavelength equal to or greater than 400 nm, wherein said light is emitted by a light source and controlling the light source and the heater pedestal using a controller.

Method of and apparatus for active energy assist baking

In the formation of an interconnect structure, a metal feature is formed in a dielectric layer. An etch stop layer (ESL) is formed over the metal feature and the dielectric layer using a precursor and a carbon-source gas including carbon as precursors. The carbon-source gas is free from carbon dioxide (CO). The precursor is selected from the group consisting essentially of 1-methylsilane (1MS), 2-methylsilane (2MS), 3-methylsilane (3MS), 4-methylsilane (4MS), and combinations thereof.

Low-k Cu barriers in damascene interconnect structures

A Ultra-Violet (UV) treatment is performed on an exposed surface of a low-k dielectric layer and an exposed surface of a metal line. After the UV treatment, an organo-metallic soak process is performed on the exposed surface of the low-k dielectric layer and the exposed surface of the metal line. The organo-metallic soak process is performed using a process gas including a metal bonded to an organic group.

Surface treatment in the formation of interconnect structure

An integrated circuit structure including reflective metal pads is provided. The integrated circuit structure includes a semiconductor substrate; a first low-k dielectric layer overlying the semiconductor substrate, wherein the first low-k dielectric layer is a top low-k dielectric layer; a second low-k dielectric layer immediately underlying the first low-k dielectric layer; and a reflective metal pad in the second low-k dielectric layer.

Curing low-k dielectrics for improving mechanical strength

A method includes forming an etch stop layer over and contacting a gate electrode of a transistor, forming a sacrificial layer over the etch stop layer, and etching the sacrificial layer, the etch stop layer, and an inter-layer dielectric layer to form an opening. The opening is then filled with a metallic material. The sacrificial layer and excess portions of the metallic material over a top surface of the etch stop layer are removed using a removal step including a CMP process. The remaining portion of the metallic material forms a contact plug.

Process for forming contact plugs

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Hsin-Chu, Taiwan

Shwang-Ming Jeng