Advanced Semiconductor Engineering, Inc.

Shuo-Hsun Chang

Chi-Chih Huang

Shu-Luan Chan

Sheng-Ming Wang

Chih-Cheng Chen

Kuo-Hua Chang

A substrate structure is disclosed. The substrate structure includes a core substrate, an interconnection portion and a solder mask. The core substrate includes a top surface and a bottom surface opposite the top surface. A circuit pattern is disposed on the top surface. The interconnection portion is disposed on the top surface; herein the interconnection portion includes a surface dielectric layer and a surface circuit layer disposed on the surface dielectric layer. The surface circuit layer is electrically connected to the circuit pattern. The solder mask is disposed on the interconnection portion; herein the solder mask includes a hole to identify the substrate structure. Besides, a method for manufacturing the substrate structure is disclosed.

Substrate strip and substrate structure and method for manufacturing the same

A substrate structure is disclosed. The substrate structure includes a core substrate, an interconnection portion and a solder mask; herein the core substrate includes a top surface and a bottom surface opposite the top surface. A circuit pattern is disposed on the top surface. The interconnection portion is disposed on the top surface; herein the interconnection portion includes a surface dielectric layer and a surface circuit layer disposed thereon. The surface circuit layer is electrically connected to the circuit pattern, and the surface dielectric layer includes at least a hole that is not covered with the surface circuit layer. The solder mask is disposed on the interconnection portion; herein the solder mask includes an indentation disposed above the hole. In addition, a method for manufacturing the substrate structure is disclosed.

Substrate structure and method for manufacturing the same

A method for forming metal bumps is disclosed. Steps of the method include supplying a substrate containing a plurality of pads; forming a first photoresist layer on the substrate, herein the first photoresist layer covers the pads; performing a planarization step to remove a portion of the first photoresist layer so as to expose the pads; forming a conductive layer on the first photoresist layer and the pads; electroplating a metal layer on the conductive layer; forming a patterned second photoresist layer on the metal layer; a portion of the metal layer and the conductive layer which are not covered by the patterned second photoresist layer is removed by using the patterned second photoresist layer as a mask; removing the patterned second photoresist layer; and forming a solder mask on the substrate, wherein the solder mask has a plurality of openings to expose the metal layer located on the pads.

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Zhongli, Taiwan

Shuo-Hsun Chang