Tokyo Shibaura Denki Kabushiki Kaisha

Kabushiki Kaisha Toshiba

Tokyo Shibaura Electric Co., Ltd.

Toyko Shibaura Electric Co., Ltd.

Shunichi Hiraki

Toshio Yonezawa

Yoshiro Baba

Yutaka Koshino

Kuniaki Kumamaru

Akihiko Osawa

Masaharu Aoyama

Satoshi Yanagiya

Tatsuo Akiyama

Takashi Ajima

Masafumi Miyagawa

Yoshitami Oka

Hidekuni Ishida

Seiji Yasuda

Hiroshi Kinoshita

Shigeo Koguchi

Yoshikazu Usuki

Kazuhiro Takimoto

Shigeo Yawata

Noburo Matsuda

Kiyoshi Kikuchi

Shoichi Kitane

In a semiconductor device including a composite substrate formed by bonding first and second semiconductor substrates to each other through an oxide film and an insulator isolation trench formed from a major surface of the first semiconductor substrate to reach the oxide film and to surround an element forming region, when the potential of the second substrate is set at a potential higher than the minimum potential in the element forming region of the first substrate, an breakdown voltage can be increased. In a semiconductor integrated circuit having an element isolation region, a semiconductor device of a perfect dielectric isolation structure having an element forming region having a thickness smaller than that of the element forming region of a P-N junction isolation structure is used to reduce, e.g., a base curvature influence, thereby obtaining a further high breakdown voltage.

Semiconductor device and method of increasing device breakdown voltage

A vertical MOSFET includes a trench whose inner surface is covered with an insulating layer having a multilayer structure. In order to reduce a change in a gate threshold voltage, and equivalent silicon dioxide thickness of the gate insulating layer and a radius of curvature of an upper corner of the trench are provided such that a dielectric breakdown electric field strength of the gate insulating layer at the upper corner is in the range of 2.5 MV/cm to 5.0 MV/cm.

Vertical MOSFET having trench covered with multilayer gate film

A power MOS semiconductor device, such as a vertical MOSFET, IGBT, and IPD, includes a body of semiconductor material having a first semiconductor layer having a first conductivity type, a second semiconductor layer having a second conductivity type and formed in the first semiconductor layer to provide a channel, a third semiconductor layer having the first conductivity type and formed in the second semiconductor layer, a trench formed in the first semiconductor layer across the third and second semiconductor layers, a gate insulating film covering a surface of the trench and extending to a surface of the third semiconductor layer, a gate electrode layer provided on the gate insulating film, and a buried layer having the first conductivity type provided in the first semiconductor layer so as to be contiguous to a bottom of the trench.

Power semiconductor device having gate structure in trench

A vertical MOS transistor comprises a semiconductor substrate, a first impurity region defined on the surface of the semiconductor substrate, a second impurity region defined under the first impurity region, the conduction type of the second impurity region being opposite to that of the first impurity region, a trench engraved on the surface of the semiconductor substrate to cut through the first and second impurity regions deeper than at least the bottom of the second impurity region, and a gate electrode disposed in the trench with a gate insulation film interposing between the wall of the trench and the gate electrode. The gate insulation film is thicker on the bottom of the trench and on part of the side walls of the trench continuous to the bottom than on the other parts.

Method of production of vertical MOS transistor

A vertical MOS transistor comprises a semiconductor substrate, a first impurity region defined on the surface of the semiconductor substrate, a second impurity region defined under the first impurity region, the conduction type of the second impurity region being opposite to that of the first impurity region, a trench engraved on the surface of the semiconductor substrate to cut through the first and second impurity regions deeper than at least the bottom of the second impurity region, and a gate electrode disposed in the trench with a gate insulation film interposing between the wall of the trench and the gate electrode. THE gate insulation film is thicker on the bottom of the trench and on part of the side walls of the trench continuous to the bottom than on the other parts.

Vertical MOS transistor and its production method

A first insulative film is formed with predetermined height and thickness in a loop shape on the surface of the Schottky-junction semiconductor substrate. A gate electrode metal film is formed with a predetermined height and thickness in a loop shape on the surface of the substrate along the inner surface of the first insulative film. A second insulative film is formed with a predetermined height and thickness in a loop shape on the surface of the substrate along the inner surface of the metal film. A channel consisting of a low concentration impurity layer, is formed in a loop shape inside the substrate directly under the metal film and the first and second insulative films. The source region consists of a high-concentration impurity layer formed such that it surrounds the channel positioned inside the substrate on the outside of the first insulative film. The drain region consists of a high-concentration impurity layer, which is formed such that it is surrounded by the channel positioned inside the substrate on the inside of the second insulative film.

Process for manufacturing a Schottky FET device using metal sidewalls as

A semiconductor device which has a protective film having a high blocking capacity against contaminating ions and a high shielding effect against an external electric field. The protective film is formed on a surface of the semiconductor device. The protective film consists essentially of an amorphous or polycrystalline silicon carbide which contains at least one element selected from the group consisting of hydrogen, nitrogen, oxygen and a halogen.

Process of producing a semiconductor device

A semiconductor device comprising a high voltage withstanding vertical MOSFET and a low voltage withstanding element both formed on a single chip. A buried layer of a high impurity concentration is formed in a region where the vertical MOSFET is formed, and another buried layer of a high impurity concentration is formed in a region where the low voltage withstanding element is formed. These buried layers have different thickness, whereby the series resistance of a circuit adjacent to the vertical MOSFET is reduced without lowering the withstand voltage of the vertical MOSFET.

Semiconductor device monolithically comprising a V-MOSFET and bipolar

A method of manufacturing a semiconductor device which comprises the step of applying a silicon carbide film having a prescribed perforated pattern as a masking film selectively to etch a silicon dioxide film or diffuse an impurity into a substrate.

Method of manufacturing a semiconductor device

A semiconductor device comprising a substrate means, a semiconductor layer of an N conductivity type formed on the substrate means, a first semiconductor region of a P conductivity type formed in the semiconductor layer and having its exposed major surface, a second semiconductor region of the N conductivity type formed in the first semiconductor region and having its exposed major surface, a first insulation layer means having a positive polarity type of charge and formed on the N semiconductor layer, and a second insulation layer means having a negative polarity type of charge and formed on the P semiconductor region.

Semiconductor device with multi-layered structure

A method of manufacturing a GaAs FET is disclosed. In this manufacturing method, a protection film is formed on a GaAs substrate and a dummy gate electrode is formed thereon. A channel length setting film is isotropically formed on the dummy gate electrode to have a constant thickness. Then, an impurity is ion-implanted in the channel length setting film. Thereafter, the channel length setting film is removed. An etching preventive film is anisotropically formed along a substantially vertical direction with respect to the GaAs substrate. The dummy gate electrode is etched using the etching preventive film as a mask so as to form a first opening in the etching preventive film. Then, a second opening is formed in the region of the protection film corresponding to the region in which the dummy gate electrode was present. A gate electrode is formed to be in contact with the GaAs substrate through the first and second openings.

A process for producing a semiconductor device by which the minority carrier lifetime can be selectively changed in a semiconductor device. A radiation beam is irradiated onto the surface of a semiconductor substrate to shorten the minority carrier lifetime. Then ions are selectively implanted into a region in which the minority carrier lifetime is to be recovered. Finally, the resultant structure is annealed.

Method of making integrated devices having long and short minority

A semiconductor memory device is disclosed which comprises:

Semiconductor memory device

A semiconductor device comprises a semiconductor body of one conductivity type, at least one semiconductor region of the opposite conductivity type formed in the semiconductor body and having a surface flush with the surface of the semiconductor body, an insulative or semi-insulative film formed on the semiconductor body or semiconductor region through a passivation layer and having a fixed charge, positive or negative, and an electrode metal layer connected to at least one of the semiconductor body and region and formed locally on the film directly or through a passivation layer. The semiconductor body or region is of N conductivity type when the film has a positive fixed charge and of P conductivity type when the film has a negative fixed charge.

Semiconductor device with selective nitride layer over channel stop

A method for producing a semiconductor element which can form a deep P-type impurity region by a diffusion of aluminum. A porous alumina layer is first formed on a semiconductor substrate. Then, a diffusion-protective layer formed of a material having a large oxygen-diffusion-inhibiting ability such as Al.sub.2 O.sub.3 is formed on the porous alumina layer. Subsequently, aluminum ions are implanted in the porous alumina layer through the diffusion-protective layer. Thereafter, a heat treatment is performed to diffuse the aluminum of the aluminum ion-implanted region in the semiconductor substrate, and a P-type impurity region is formed. Alternatively, a porous alumina layer is formed on the semiconductor substrate, and an aluminum layer is then formed thereon. The diffusion-protective layer is formed on the aluminum layer, and a heat treatment is then performed, thereby diffusing the aluminum forming the aluminum layer in the semiconductor substrate, and a P-type impurity region is thus formed.

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Yokohama, Japan

Shunichi Hiraki