Taiwan Semiconductor Manufacturing Comp. Ltd.

United Microelectronics Corp.

Shun-Liang Hsu

Ruey-Hsin Liu

Chen-Bau Wu

ChaoChieh Tsai

You-Kuo Wu

Tsung-Yi Huang

Puo-Yu Chiang

Mou-Shiung Lin

Yu-Chang Jong

Jyh-Kang Ting

Chien-Shao Tang

Chun-Yi Shih

Robin Hsieh

Yen-Ming Chen

Yung-Lung Hsu

Hsin-Hui Lee

Kai-Ming Ching

Fu-Hsin Chen

Yean-Kuen Fang

Chao-Yuan Su

Hsiu-Mei Yu

Chao-Chieh Tsai

Chia-Fu Lin

Jyh-Haur Wang

Eric Huang

Li-Chih Chen

Chyi-Chyuan Huang

Ken-Shen Chou

Fang-Cheng Lui

Edward Chiang

Syun-Ming Jang Jang

Chia-Ta Hsieh

Chung-Hui Chen

Kuo-Ming Wu

Tsu Shih

Shyh-Chyi Wong

Shih-Shiung Chen

Yuan-Chang Huang

Juing-Yi Wu

Cheng-Yu Chu

Han-Liang Tseng

Yueh-Chiou Lin

An-Min Chiang

Shaulin Shue

Chi-Hsuen Chang

Kuo-Su Huang

Chih-Feng Huang

Chang-Song Lin

Te-Yin Hsia

Ming-Dar Lei

Hsi-Chieh Chen

Hsiu-Chieh Cheng

Jyh-Min Tsaur

Chieh-Chuan Huang

Mao-Hsiung Kuo

Yu-Hsein Tsai

Chun-Yi Shi

Mou S Lin

A new method is provided for the creation of a solder bump. Conventional methods are initially followed, creating a patterned layer of Under Bump Metal over the surface of a contact pad. A layer of photoresist is next deposited, this layer of photoresist is patterned and developed creating a resist mask having a T-shape opening aligned with the contact pad. This T-shaped opening is filled with a solder compound, creating a T-shaped layer of solder compound on the surface of the layer of UBM. The layer of photoresist is removed, exposing the created T-shaped layer of solder compound, further exposing the layer of UBM. The layer of UBM is etched using the T-shaped layer of solder compound as a mask. Reflow of the solder compound results in creating a solder ball.

Method to improve bump reliability for flip chip device

A semiconductor structure includes a semiconductor substrate of a first conductivity type; a pre-high-voltage well (pre-HVW) in the semiconductor substrate, wherein the pre-HVW is of a second conductivity type opposite the first conductivity type; a high-voltage well (HVW) over the pre-HVW, wherein the HVW is of the second conductivity type; a field ring in the HVW and occupying a top portion of the HVW, wherein the field ring is of the first conductivity type; an insulation region over and in contact with the field ring and a portion of the HVW; a gate electrode partially over the insulation region; a drain region in the HVW, wherein the drain region is of the second conductivity type; and wherein the HVW horizontally extends further toward the drain region than the pre-HVW; and a source region adjacent to, and on an opposite side of the gate electrode than the drain region.

Lateral power MOSFET with high breakdown voltage and low on-resistance

A semiconductor device with high breakdown voltage and low on-resistance is provided. An embodiment comprises a substrate having a buried layer in a portion of the top region of the substrate in order to extend the drift region. A layer is formed over the buried layer and the substrate, and high-voltage N-well and P-well regions are formed adjacent to each other. Field dielectrics are located over portions of the high-voltage N-wells and P-wells, and a gate dielectric and a gate conductor are formed over the channel region between the high-voltage P-well and the high-voltage N-well. Source and drain regions for the transistor are located in the high-voltage P-well and high-voltage N-well. Optionally, a P field ring is formed in the N-well region under the field dielectric. In another embodiment, a lateral power superjunction MOSFET with partition regions located in the high-voltage N-well is manufactured with an extended drift region.

A transistor suitable for high-voltage applications is provided. The transistor is formed on a substrate having a deep well of a first conductivity type. A first well of the first conductivity type and a second well of a second conductivity type are formed such that they are not immediately adjacent each other. The well of the first conductivity type and the second conductivity type may be formed simultaneously as respective wells for low-voltage devices. In this manner, the high-voltage devices may be formed on the same wafer as low-voltage devices with fewer process steps, thereby reducing costs and process time. A doped isolation well may be formed adjacent the first well on an opposing side from the second well to provide further device isolation.

High voltage CMOS devices

A semiconductor device. The semiconductor device comprises an isolation structure and two heavily doped regions of a second conductivity type spaced apart from each other by the isolation structure. The isolation structure comprises an isolation region in a semiconductor substrate and a heavily doped region of the first conductivity type. The isolation region has an opening and the heavily doped region of the first conductivity type is substantially surrounded by the opening of the isolation region.

Isolation structure in field device

In one embodiment, the disclosure relates to a method and apparatus for surface recovery of a polymer insulation layer through implantation. The method includes providing a substrate having thereon a conductive pad and an insulation layer, optionally processing the conductive pad to remove oxide layer formed on the conductive pad and conducting ion implantation to recover dielectric properties of the insulation layer.

Method and apparatus for polymer dielectric surface recovery by ion implantation

A semiconductor structure with high-voltage sustaining capability. A semiconductor structure with high-voltage sustaining capability includes a first well region of a first conductivity type. A pair of second well regions of a second conductivity type opposite to the first conductivity type are respectively disposed adjacent to the first well region and an anti-punch through region of the first conductivity type is disposed in at least the lower portion of the first well region to increase the doping concentration therein. Due to the ion supplementation of the anti-punch through region, the size of a semiconductor structure can be further reduced without affecting the HV sustaining capability and undesired effects such as punch-through effects can be prevented.

Semiconductor structure with high-voltage sustaining capability and fabrication method of the same

A high-voltage MOS device includes a first high-voltage well (HVW) region overlying a substrate, a second HVW region overlying the substrate, a third HVW region of an opposite conductivity type as that of the first and the second HVW regions overlying the substrate, wherein the HVPW region has at least a portion between the first HVNW region and the second HVNW region, an insulation region in the first HVNW region, the second HVNW region, and the HVPW region, a gate dielectric over and extending from the first HVNW region to the second HVNW region, a gate electrode on the gate dielectric, and a shielding pattern electrically insulated from the gate electrode over the insulation region. Preferably, the gate electrode and the shielding pattern have a spacing of less than about 0.4 &#x3bc;m. The shielding pattern is preferably connected to a voltage lower than a stress voltage applied on the gate electrode.

Shielding structures for preventing leakages in high voltage MOS devices

A semiconductor device includes a substrate having a source, a drain, and a gate between the source and the drain. Both the source and the drain include a first edge, and the gate includes a first portion. A first deep trench structure is situated under the first portion of the gate and proximate to the first edge of the source and the first edge of the drain.

High voltage semiconductor device utilizing a deep trench structure

A transistor of an integrated circuit is provided. A first doped well region is formed in a well layer at a first active region. At least part of the first doped well region is adjacent to a gate electrode of the transistor. A recess is formed in the first doped well region, and the recess preferably has a depth of at least about 500 angstroms. A first isolation portion is formed on an upper surface of the well layer at least partially over an isolation region. A second isolation portion is formed at least partially in the recess of the first doped well region. At least part of the second isolation portion is lower than the first isolation portion. A drain doped region is formed in the recess of the first doped well region. The second isolation portion is located between the gate electrode and the drain doped region.

Integrated circuit transistor insulating region fabrication method

Growing community of inventors

Hsin-Chu, Taiwan

Shun-Liang Hsu