Lsi Logic Corporation

Lsi Corporation

Shumay X Dou

Joe W Zhao

Keith K Chao

Nicholas F Pasch

Colin D Yates

Wilbur G Catabay

Philippe Schoenborn

Kai Zhang

Dilip Vijay

Masaichi Eda

Rongxiang Hu

Yongbae Kim

Sang-Yun Lee

Hiroaki Takikawa

Sarah Neuman

Nicholas K Eib

Dawn M Lee

Richard S Osugi

Marilyn Hwan

A method for forming a dual damascene interconnect in a dielectric layer is provided. Generally, a first aperture is etched in the dielectric. A poison barrier layer is formed over part of the dielectric, which prevents resist poisoning. A patterned mask is formed over the poison barrier layer. A second aperture is etched into the dielectric layer, wherein at least part of the first aperture shares the same area as at least part of the second aperture.

Method of preventing resist poisoning in dual damascene structures

Increased resolution is available from acid-catalyzed photoresist used in fabricating integrated circuits by inhibiting chemically-basic contaminants from contacting the photoresist placed above an IC structure which emits those chemically-basic contaminants. The inhibition can result from physical barrier characteristics of a barrier layer placed between the contaminant-emitting surface and the overlying layer of photoresist, or the layer of barrier material may contain acid moieties which chemically neutralize the emitted chemically-basic contaminants before the contaminants reach the photoresist.

Method of protecting acid-catalyzed photoresist from chip-generated basic contaminants

The system and method performs optical proximity correction on an integrated circuit (IC) mask design by initially performing optical proximity correction on a library of cells that are used to create the IC. The pre-tested cells are imported onto a mask design. All cells are placed a minimum distance apart to ensure that no proximity effects will occur between elements fully integrated in different cells. A one-dimensional optical proximity correction technique is performed on the mask design by performing proximity correction only on those components, e.g., lines, that are not fully integrated within one cell.

System and method for performing optical proximity correction on the interface between optical proximity corrected cells

Provided is a method and composition for obtaining consistent alignment mark profiles with both detectibiliy and detection accuracy for use in conjunction with CMP planarization processes in semiconductor fabrication. The method involves physical vapor deposition of metal over an angled, metal-lined alignment mark trench in the surface of a semiconductor wafer following wafer planarization by CMP. The shape of the trench creates a shadowing effect which produces minimal deposition in the angled region of the trench and overcomes asymmetric metal loss due to attack from slurry accumulating in the trench during CMP. The result is the formation of a reliable and reproducible alignment mark.

Consistent alignment mark profiles on semiconductor wafers using PVD shadowing

Provided is a method and composition for protecting alignment mark trench walls from attack by CMP slurry accumulating in an alignment mark trench during CMP processing. In a preferred embodiment, a metal organic chemical vapor deposition titanium nitride (MOCVDTiN) layer is deposited over a conventionally applied bulk tungsten layer prior to commencing CMP operations. This MOCVDTiN layer is resistant to CMP slurry attack. As a result, the tungsten trench profile remains a consistent and reliable alignment mark.

Consistent alignment mark profiles on semiconductor wafers using metal

Provided is a method and composition for reducing the rate of, and rendering more uniform the oxidation of alignment mark trench side walls by CMP slurry accumulating in an alignment mark trench during CMP processing. In a preferred embodiment, a nucleation layer of tungsten having an equiaxed grain structure with fine grain size and conformity is deposited over a conventionally applied bulk tungsten layer prior to commencing CMP operations. The fine grain size and equiaxed grain structure of this nucleation layer make it more resistant and more uniform in response to slurry attack. As a result, the tungsten trench profile remains a consistent and reliable alignment mark.

Consistent alignment mark profiles on semiconductor wafers using fine

Consistent alignment mark profiles on semiconductor wafers using PVD

A method of providing etched alignment marks on a semiconductor workpiece that has a substantially planar surface, such as one that has been polished, for supporting accurate alignment of the workpiece in subsequent process operations. The surface of the semiconductor workpiece includes two layers of materials that abut at the workpiece surface. For example, the workpiece may include a layer of insulative material such as silicon dioxide forming several vias and a layer of conductive material such as tungsten forming plugs in the vias. The method includes etching the substantially planar surface to reduce a height of one of the materials below the height of the other material. For example, the tungstein plugs can be etched to a height that is below the height of the surrounding silicon dioxide. The location where the silicon dioxide abuts the tungsten produces a small bump. This bump then serves as an alignment mark for subsequent operations. Furthermore, such subsequent operations will replicate, and/or enhance, the topographical distinction of the alignment mark.

Alignment mark contrast enhancement

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San Jose, CA, United States of America

Shumay X Dou