Hitachi, Ltd.

Hitachi-high-technologies Corporation

Renesas Technology Corp.

Elpida Memory, Inc.

Hitachi Electronics Engineering Co., Ltd.

Renesas Technology Corp & Hitachi Ulsi Systems Co., Ltd.

Shuji Kikuchi

Tadanobu Toba

Katsunori Hirano

Yuji Sonoda

Wen Zheng Li

Hideyuki Aoki

Iwao Suzuki

Ikuo Kawaguchi

Yuichi Sakurai

Fumie Kobayashi

Mitsuaki Katagiri

Ichiro Anjo

Takeshi Wada

Yasuhiro Gunji

Masayuki Takahashi

Yoshiro Gunji

Akira Karakama

Masaaki Inadachi

Takashi Kanesaka

Chisato Hamabe

Yoshio Ouchida

Kanji Furuhashi

Ryohei Kamiya

An inspection device carries out beam scanning on a stable scanning cycle by enabling flexible change of various scanning sequences according to inspection conditions thereof, and at the same time, eliminates as much unevenness as possible in scanning cycle which hinders stabilization of charging. A beam scanning scheduler schedules beam scanning based on an inputted scanning condition, and a programmable sequencer carries out beam scanning control according to a beam scanning schedule generated by the beam scanning scheduler. The scanning scheduler calculates scanning line reference coordinates on a scanning-line-by-scanning-line basis, based on the scanning condition, and issues a scanning cycle trigger. The programmable sequencer controls supply timing of the scanning line reference coordinates and a scanning position on an in-line pixel-by-pixel basis, based on line scanning procedure information and the scanning cycle trigger provided from the beam scanning scheduler.

Charged particle beam device

When an inspection apparatus of a semiconductor device repeatedly executes computation of prescribed area data, such as image processing for detecting defects, procedures for commanding, data load, computation, and data store need to be repeated the number of times of the computation. This may impose a limitation on the speeding up of the operation. In addition, when performing parallel computation by a high-capacity image processing system for handling minute images, a lot of processors are needed, resulting in an increase in cost. In order to solve the above-mentioned problems, in the invention, an inspection apparatus of a semiconductor device includes a data memory including an access section which is capable of reading and writing simultaneously, a plurality of numerical computation units, a connector for connecting the data memory and the numerical computation units, a controller for collectively controlling the contents of processing by the plurality of numerical computation units, another connector for connecting the numerical computation units and the controller, and a data transfer controller for controlling data transfer between the numerical computation units.

Method and apparatus for inspecting defects of semiconductor device

The present invention has a subject to provide an apparatus that optimizes scanning in accordance with circumstances or purposes, reduces distortion of images, and improves throughput, image quality, and defect detection rate by controlling deflection of a charged particle beam in a stage tracking system. To solve this subject, an apparatus according to the present invention is an inspection apparatus for detecting abnormal conditions of an inspection target by irradiating the inspection target with the charged particle beam and detecting generated secondary electrons, including both a stage that moves continuously with the inspection target placed thereon and a deflection control circuit for providing a deflector with a scanning signal that causes the charged particle beam to scan repeatedly in a direction substantially perpendicular to a stage movement axis direction while the charged particle beam being deflected in the stage movement axis direction in accordance with a change in movement speed of the stage during movement of the stage.

Charged particle beam apparatus, and image generation method with charged particle beam apparatus

A semiconductor inspecting apparatus includes: a buffer memory whose width is matched to the greater of parallel bus width and the width of the number of serial lanes; a preceding stage bus switching unit that fills the buffer memory with input data without making a free space; equivalent transmission capacity conversion including a following stage bus switching unit that fills read data to the width of an arbitrary number of serial lanes without making a free space; a preceding stage bus switching unit that fills a buffer memory with input data without making a free space; and equivalent transmission capacity inverse conversion including a following stage bus switching unit that fills a parallel bus of arbitrary width with data read from a buffer memory without making a free space.

Semiconductor inspecting apparatus

The present invention relates to a DRAM stacked packages, a DIMM, a method for testing them, and a semiconductor manufacturing method. According to the present invention, there is provided a DRAM stacked package comprising: a plurality of stacked DRAMs; external terminals to which test equipment is connected, said external terminals being used to input/output at least address, command, and data; and an interface chip provided between said plurality of stacked DRAMs and said external terminals. The plurality of DRAMs and the interface chip are implemented on a package. The interface chip comprises: a test circuit including: an algorithmic pattern generator for generating a test pattern used to test the plurality of DRAMs; applying circuits for applying said generated test pattern to the plurality of DRAMs; and a comparator for comparing each response signal received from the plurality of DRAMs with an expected value for judgment.

DRAM stacked package, DIMM, and semiconductor manufacturing method

A testing circuit using ALPG is mounted in a testing board in which sockets for mounting semiconductor memories as devices to be tested in the board is mounted and a volatile memory for storing a data table for generating a random pattern is provided in the testing circuit so that a test using a test pattern having no regularity is performed using the data table in addition to a test using a test pattern having regularity generated by the ALPG.

Testing board for semiconductor memory, method of testing semiconductor memory and method of manufacturing semiconductor memory

Semiconductor testing equipment according to the present invention comprises: an algorithmic pattern generator for generating a test pattern for testing a memory under test and applying the pattern to the memory under test; a comparator for comparing a response signal from the memory under test and an expected value from tho algorithmic pattern generator; a fail address acquisition part for storing an address of the memory under test (fail address) when a result compared by the comparator is failed; a fail address analysis part for analyzing the failed address and calculating the address to be repaired (repair address); and a cycle-pattern generator for redundancy processing for inserting the address to be repaired into a test pattern and applying the address to the memory under test, so that even when capacity of the semiconductor memory is increased, a fabrication yield thereof is raised by testing the memory after the packaging and by performing the redundancy processing of a defective.

Semiconductor testing equipment, testing method for semiconductor, fabrication method of semiconductor, and semiconductor memory

A signature circuit, i.e., a random-number generating circuit, is provided in a memory test apparatus. Also, a signature circuit is provided in each of devices-under-test. This configuration allows the large number of semiconductor integrated-circuit devices to be tested at one time with a high efficiency. This condition realizes a tremendous reduction in the test cost.

Semiconductor device, and the method of testing or making of the semiconductor device

To speed up the pattern generator which is a bottleneck for speedup of an LSI tester, a continuous address control information for generating addresses for continuous pattern memory read is generated at a speed 1/N (N is an optional number larger than 1) times the operation speed of the continuous address generator, and the address controller is divided into a 1st and a 2nd address controller. The two controllers are connected via a buffer memory to ensure the normal operation when the correspondence between address control instructions and patterns to be continuously read is not 1:N. Continuous address information generated by the 1st address controller is stored in the buffer memory. The second address controller, which actually generates continuous addresses, receives the continuous address information from the buffer memory, outputs the addresses to the pattern memory at a speed N times of the operation speed of the 1st address controller, and receives the next continuous address information from the buffer memory once again when the continuous address generation is finished to repeat the operation mentioned above.

IC tester

A pattern generator permitting to output patterns at high speed and having an operating function, which is suitable for generating test patterns for memory ICs. Although it was known heretofore to increase the operating speed by operating a plurality of pattern generators, for which patterns were generated from memories, in which patterns were previously stored, in parallel, it was not possible to operate pattern generators having an operating function in parallel. A method, by which the order of execution of operation processing instructions is assigned to each of the pattern generators and operation processing instructions are accumulated and allows patterns to be generated at high speed by means of a pattern generator having an operating function. Specifically, the operating processing instructions are grouped and rearranged such that all the pattern generators execute instructions in parallel.

Pattern generator having plural pattern generating units executing

Test pattern generator

Growing community of inventors

Yokohama, Japan

Shuji Kikuchi