Sanyo Electric Co., Ltd.

Semiconductor Components Industries, LLC

Shuji Fujiwara

Masao Nakao

Hiroaki Furukawa

Ryokan Yuasa

Masaaki Nemoto

Richard Burton

Kiyofumi Nakaya

Seiichi Tokunaga

Ryohkan Yuasa

Tatsuhiko Koide

Tetsuro Hirano

An electrostatic discharge robust semiconductor transistor (transistor) includes a semiconductor substrate of a first conductivity type, a substrate contact region of the first conductivity type coupled with the semiconductor substrate, a source region of a second conductivity type, a channel region of the second conductivity type, a gate region of the first conductivity type, a drain region having a first drain region of the first conductivity type and a second drain region of the second conductivity type, and an electrical conductor coupled over the second drain region and a portion of the first drain region. A portion of the first drain region not covered by the electrical conductor forms a resistive electrical ballast region configured to protect the transistor from electrostatic discharge (ESD) induced voltage pulses. In implementations the transistor includes a silicon controlled rectifier (SCR) junction field effect transistor (SCR JFET) or a laterally diffused metal-oxide semiconductor (SCR LDMOS).

Electrostatic discharge (ESD) robust transistors and related methods

An ESD tolerance of an LDMOS transistor is improved. An N+ type source layer shaped in a ladder and having a plurality of openings in its center is formed in a surface of a P type base layer using a gate electrode and a resist mask. A P+ type contact layer is formed to be buried in the opening. At that time, a distance from an edge of the opening, that is an edge of the P+ type contact layer, to an edge of the N+ type source layer is set to a predetermined distance. The predetermined distance is equal to a distance at which an HBM+ESD tolerance of the LDMOS transistor, which increases as the distance increases, begins to saturate.

Electrostatic discharge (ESD) tolerance for a lateral double diffusion metal oxide semiconductor (LDMOS) transistor

An electrostatic discharge failure protective element () is provided with second conductivity type source region () and drain region (), which are formed at a prescribed interval to sandwich a channel region () on the surface of a first conductivity type semiconductor substrate (); a first conductivity type well region () formed to cover the source region; a second conductivity type buried layer () formed below the first conductivity type well region; a second conductivity type first impurity region () formed between the drain region and the buried layer to constitute a current path; and a second conductivity type second impurity region () to isolate the well region and the semiconductor substrate one from the other.

Electrostatic discharge failure protective element, electrostatic discharge failure protective circuit, semiconductor device and semiconductor device manufacturing method

A semiconductor device provided with an emitter layer having a narrowed base contact portion. The semiconductor device includes a collector layer arranged on a semiconductor substrate. A conductive layer is arranged on the collector layer. A silicon film is arranged on the conductive layer. An emitter electrode is arranged on the silicon film. A first film covers the side of the emitter electrode. The silicon film includes a first region contacting the emitter electrode and a second region differing from the first region. A contact surface between the first region and the emitter electrode is located at a level that is higher than that of the lower surface of the first film. At least part of the second region of the silicon film is located between the conductive layer and the first film and is in contact with the conductive layer and the first film.

Semiconductor device

A semiconductor device including a bipolar transistor in which the collector resistance. The bipolar transistor includes a first conduction type semiconductor substrate having a main surface. A second conduction type collector region is formed in the semiconductor substrate. A shallow trench isolation structure isolates the main surface of the semiconductor substrate into two insulated active regions. A collector leading portion is formed in one of the active regions. A first conduction type base region and a second conduction type emitter region are formed on the other one of the active regions. The collector region has a first depth from the main surface immediately below the shallow trench isolation structure, and the collector region has a second depth from the main surface immediately below the two active regions. The first depth is less than the second depth.

Semiconductor bipolar transistor

A desired pattern is formed on a non-superconducting oxide film after the non-superconducting oxide film has been formed on a magnesia substrate. A superconducting oxide film is formed over the exposed parts of the substrate and the non-superconducting oxide film. The epitaxial orientation of the superconducting oxide film section on the non-superconducting oxide film is different from that of the superconducting oxide film section on the substrate. A tilt-boundary junction is produced at a boundary between the superconducting film sections which are different in epitaxial orientation from each other. Thus, a Josephson junction having a desired pattern can be obtained.

Process of making high T.sub.c Josephson junction device

An oxide film having a desired pattern is first formed on a magnesia substrate. A superconducting oxide film is then formed on the exposed portion of the magnesia substrate and also on the oxide film. Thus, a tilt-boundary junction is formed in the boundary between the superconducting oxide film portion on the magnesia substrate and the superconducting oxide film portion on the oxide film. The tilt-boundary junction functions as a Josephson junction. By utilizing the Josephson junction in the tilt-boundary junction, a SQUID pattern can be formed on the magnesia substrate to provide a SQUID device.

Process of making squid device having tilt-boundary junction

An ion beam is irradiated to an oxide superconducting thin film formed on a substrate to disturb the crystal structure of the superconducting thin film and thus forming a damaged layer. The damaged layer has higher solubility in a halogen solution has a faster etching rate than other portions. Then, the superconducting thin film is etched by using a halogen solution to remove the damaged layer and form a groove at that portion. As a result, a groove of a desired form can be provided efficiently.

Method for processing superconducting thin films

A method of forming a fine groove on a superconducting thin film. A superconducting oxide thin film is formed on a MgO substrate, and a damaged layer is formed thereon by irradiating the superconducting thin film with focused ion beams to such a degree that not sputter is generated and the crystalline structure of the superconducting thin film is disturbed. The damaged layer is then removed by treatment with a strong alkali such as KOH. Thus, a fine groove is effectively formed. By inserting an oxide layer between the substrate and the superconducting thin film, a Josephson junction device suitable for superconducting transistors is produced.

Growing community of inventors

Hashima, Japan

Shuji Fujiwara