Nec Corporation

Nippon Electric Co., Ltd.

Shuji Asai

Michihisa Suga

Daisuke Manabe

Hirokazu Oikawa

Michihisa Kohno

A semiconductor element and a circuit thereof are formed on the front surface of a semiconductor substrate of a semiconductor device and are protected with an insulating film. An opening is bored that penetrates from the front surface to the back surface of the substrate at a predetermined position of the substrate. A buried wiring line of a metal film, which becomes a semiconductor substrate penetrative conductor, is formed on the inner surface of the opening. The space enclosed by the buried wiring line is filled with a resin film. A grounding pad or a terminal pad is disposed at a predetermined position on the back surface of the semiconductor substrate.

Semiconductor device and method for manufacturing the same

A compound semiconductor device having improved backgate voltage resistance characteristics. To improve the backgate voltage resistance of a compound semiconductor device having field effect transistors on a main surface of a semi-insulating substrate, boron ions are implanted on the rear surface to form a defect-rich layer having carrier recombination centers.

Compound semiconductor device having an ion implanted defect-rich layer for improved backgate effect suppression

In a method of manufacturing a semiconductor device which has a semiconductor substrate, a channel layer formed on the semiconductor substrate and an insulating film deposited on the channel layer, an opening corresponding to a gate electrode pattern is formed in the insulating film by the use of a photoresist film. The channel layer contains crystal components while the photo-resist film contains carbon. The insulating film is etched to exposed said channel layer after removing the photoresist film. In consequence, no reacted production is formed between the crystal components and the carbon on the exposed channel layer.

Method of manufacturing semiconductor device

On a channel layer, there are disposed a gate electrode and a first contact layer of which a side surface is brought into contact with the gate electrode on the source side and of which a side surface is apart from the gate electrode on the drain side. Provided on the first contact layer is a second contact layer on which ohmic source and drain electrodes are arranged. A connection wiring is disposed on an upper end of the gate electrode. Specifically, there are provided a thin contact layer and a thick contact layer such that the thin contact layer is brought into contact with the gate electrode. Therefore, the problems of the contact resistance of the ohmic electrode and the gate parasitic capacitance are removed and both drawbacks can be improved at the same time.

Method of manufacturing a field effect transistor

Field effect transistor

The invention provides a semiconductor substrate comprising a substrate of a first material and a crystal growth layer formed on the substrate, the crystal growth layer being made of compound semiconductors different from the first material wherein the substrate has a surface diffusion region being heavily doped with one or more elements of the compound semiconductors. A silicon substrate receives an ion-implantation of one or more elements constituting a compound semiconductor different except for silicon at a high impurity concentration for a heat treatment at a higher temperature than a growth temperature of the compound semiconductor and subsequent cooling down to the growth temperature of the compound semiconductor followed by crystal growth of the compound semiconductor on the substrate.

Substrate with a compound semiconductor surface layer and method for

On a semi-insulative GaAs substrate, a channel layer, an electron supply layer, a threshold voltage controlling layer, an etching stop layer, a contact layer and an insulation layer are grown. By etching the insulation layer, gate openings are formed in an E-type element region and a D-type element region. With taking the gate opening as mask, dry etching is performed for the contact layer to form openings. On the inner periphery of the openings, side wall insulation layers are formed. With masking the gate opening in the D-type element region, and with taking the side wall insulation layer as mask, the etching stop layer is etched by wet etching, and threshold voltage controlling layer is etched by isotropic dry etching. After formation of the gate electrodes, source and drain electrodes are formed. By this, damaging of crystal upon formation of recess portion by etching is eliminated to prevent degradation of characteristics. Also, a source resistance can be lowered.

Fabrication process for compound semiconductor device

A sintered high sensitive electrophotographic plate free of cracks in a photoconductive layer and exfoliation of it from a substrate can be obtained by adding an inorganic material, whose melting or softening temperature is higher than a firing temperature, into a mixture composed essentially of photoconductive material and a glass binder having a softening temperature lower than the firing temperature.

Growing community of inventors

Tokyo, Japan

Shuji Asai