Kabushiki Kaisha Toshiba

Toshiba Memory Corporation

Shuichi Toriyama

Kenichi Murooka

Tomoya Kawai

Yoshiaki Fukuzumi

Haruki Toda

Masumi Saitoh

Naoki Yasuda

Reika Ichihara

Tatsuya Ohguro

Yuichiro Mitani

Hiroki Sasaki

Satoru Takase

Koichi Kokubun

Shintaro Nakano

Kazuya Matsuzawa

Tomonori Kurosawa

Takashi Ishida

Yusuke Higashi

Haruka Sakuma

Hideto Horii

According to one embodiment, a semiconductor memory device includes a first interconnect layer, a first insulating layer, a second interconnect layer, and a memory pillar including a second insulating layer, a charge storage layer, and a third insulating layer stacked on a part of a side surface and on the bottom surface of the memory pillar, and a first silicide layer in contact with the first interconnect layer, a semiconductor layer, and a second silicide layer stacked in order along a first direction. A height position of a bottom surface of the first silicide layer is lower than a top surface of the first interconnect layer, and a height position of a top surface of the first silicide layer is higher than a bottom surface of the second interconnect layer.

Semiconductor memory device

A nonvolatile semiconductor memory device according to one embodiment includes: a first wiring extending in a first direction as a longitudinal direction thereof; a second wiring extending in a second direction as a longitudinal direction thereof, the second direction intersecting with the first direction; a memory cell disposed at an intersection portion of the first wiring and the second wiring, the memory cell including a variable resistive element; a select transistor having one end connected to the second wiring; and a third wiring connected to the other end of the select transistor. A semiconductor layer included in the select transistor has a first impurity concentration at the second end. An impurity concentration of the semiconductor layer decrease to a second impurity concentration from the first impurity concentration as approaching to the first end from the second end.

Resistive memory with varying dopant concentration in select transistor channel

According to one embodiment, a semiconductor memory device includes first conductive layers extending in a first direction and stacked in a second direction intersecting the first direction, a first semiconductor layer extending in the second direction and including a material having one of a first conductivity type and a second conductivity type, a first insulation layer disposed inside the first semiconductor layer, a second conductive layer disposed inside the first insulation layer, and a variable resistance layer disposed between the first conductive layers and the first semiconductor layer.

Semiconductor memory device having local bit line with insulation layer formed therein

In a write operation to memory cells, the control unit is operative to, when a threshold voltage to be provided to a selected memory cell is not less than a reference value,

Semiconductor memory device and method of manufacturing the same

According to one embodiment, a semiconductor memory device includes a plurality of first wirings, a plurality of second wirings, a variable resistance layer, a first barrier insulating layer, and a second barrier insulating layer. The first wirings are disposed at predetermined pitches in a first direction intersecting with a substrate. The second wirings are disposed at predetermined pitches in a second direction intersecting with the first direction. The second wirings are formed to extend in the first direction. The variable resistance layer is disposed between the first wiring and the second wiring. The variable resistance layer is disposed at a position where the first wiring intersects with the second wiring. The first barrier insulating layer is disposed between the first wiring and the variable resistance layer. The second barrier insulating layer is disposed between the second wiring and the variable resistance layer.

Semiconductor memory device and method of controlling the same

A semiconductor memory device according to an embodiment comprises: a plurality of first lines extending in a first direction perpendicular to a substrate surface and arranged with a certain pitch in a second direction parallel to the substrate surface; a plurality of second lines extending in the second direction and arranged with a certain pitch in the first direction; a memory cell provided at an intersection of the first line and the second line and including a variable resistance element; a third line provided extending in the second direction between the plurality of second lines; and a control circuit capable of executing a first operation that changes a resistance value of the variable resistance element by applying a voltage to the memory cell via the first line and the second line, and a second operation that supplies heat to the memory cell using the third line.

A non-volatile semiconductor storage device according to each of the embodiments includes a cell array that includes a plurality of first wires extending in a first direction, a plurality of second wires extending in a second direction crossing the first direction, and a plurality of memory cells each provided at an intersection between each of the first wires and each of the second wires. Each memory cell includes a variable resistance film of which resistance varies depending on a state of a filament in a medium. Each cell array has a first portion at which a distance between the first wire and the second wire is minimized and a second portion at which a distance between the first wire and the second wire is larger than the first portion at the intersection between each of the first wires and each of the second wires.

Non-volatile semiconductor storage device

A memory string includes: a first semiconductor layer formed in a columnar shape extending in a stacking direction perpendicular to a substrate; a tunnel insulating film formed surrounding a side surface of the first semiconductor layer; a charge accumulation film formed surrounding the tunnel insulating film and configured to be capable of accumulating charges; a block insulating film formed surrounding the charge accumulation film; and a plurality of first conductive layers formed surrounding the block insulating film and disposed at a predetermined interval in the stacking direction. The first semiconductor layer comprises carbon-doped silicon and being formed to have different carbon concentrations in upper and lower portions in the stacking direction.

Non-volatile semiconductor memory device having carbon doped columnar semiconductor layer

According to an embodiment, a solid-state imaging device includes a photoelectric, conversion element. The photoelectric conversion element includes a first semiconductor layer, a second semiconductor layer, and a third semiconductor layer. In the solid-state imaging device, D/L&#xd7;n/N&#x3c;D/L&#xd7;n/Nand D/L&#xd7;n/N&#x3c;D/L&#xd7;n/Nare established.

Solid-state imaging device

According to one embodiment, a semiconductor memory device includes a memory cell array including blocks, each block being capable of executing a write, read, or erase operation independently of other blocks. A control portion is configured to execute the operation of a first block among the blocks in a first cycle, set a selection inhibited region within a range of a predetermined distance from the first block, until a temperature relaxation time for relaxing a temperature of the first block has elapsed, set a region except the selection inhibited region among the blocks as a second block, and execute the operation of the second block in a second cycle.

An electrically erasable programmable read-only memory (EEPROM) device of the NAND type having sideface electrodes as auxiliary electrodes on the opposite lateral surfaces of a transistor channel region to thereby improve operation margins is discusssed. The NAND EEPROM, also known as NAND flash memory, has on a semiconductive substrate an array of memory cells including a serial combination of memory cell transistors. Each of memory cell transistors has a pair of source and drain regions, a channel region, a tunnel insulator film, a charge storage layer, a control dielectric film, a control electrode, a sideface dielectric film on the sidefaces of the channel region, and sideface electrodes which are formed on the side surfaces of channel region with the channel region being laterally interposed therebetween. The sideface electrodes are commonized or 'shared' by adjacent ones of the serially coupled memory cell transistors.

Growing community of inventors

Yokohama, Japan

Shuichi Toriyama