Micron Technology Incorporated

Round Rock Research, LLC

Shuang Meng

Garo Jacques Derderian

Gurtej S Sandhu

Mirzafer K Abatchev

Paul A Morgan

Jingyi Bai

Luan C Tran

Zhiping Yin

John K Lee

D Mark Durcan

William T Rericha

Brian J Coppa

Puneet Sharma

Sheron Honarkhah

Ardavan Niroomand

Baosuo Zhou

Demetrius Sarigiannis

Ramakanth Alapati

Joseph Neil Greeley

Kyle K Kirby

Jiutao Li

Danny Dynka

John A Smythe

Shyam Surthi

Raman Alapati

Jingyi (Jenny) Bai

Joseph Neil Greely

A method for patterning a layer increases the density of features formed over an initial patterning layer using a series of self-aligned spacers. A layer to be etched is provided, then an initial sacrificial patterning layer, for example formed using optical lithography, is formed over the layer to be etched. Depending on the embodiment, the patterning layer may be trimmed, then a series of spacer layers formed and etched. The number of spacer layers and their target dimensions depends on the desired increase in feature density. An in-process semiconductor device and electronic system is also described.

Pitch reduction technology using alternating spacer depositions during the formation of a semiconductor device and systems including same

Devices such as transistors having an oxide layer that provide a depletion field in a conduction channel. A barrier layer is formed over the oxide layer. A gate electrode is formed over the barrier layer. The barrier layer and gate electrode are configured to reduce the width of the depletion field absent a voltage applied to the gate electrode.

Transistor with reduced depletion field width

A transition metal oxide dielectric material is doped with a non-metal in order to enhance the electrical properties of the metal oxide. In a preferred embodiment, a transition metal oxide is deposited over a bottom electrode and implanted with a dopant. In a preferred embodiment, the metal oxide is hafnium oxide or zirconium oxide and the dopant is nitrogen. The dopant can convert the crystal structure of the hafnium oxide or zirconium oxide to a tetragonal structure and increase the dielectric constant of the metal oxide.

High dielectric constant transition metal oxide materials

An integrated circuit having differently-sized features wherein the smaller features have a pitch multiplied relationship with the larger features, which are of such size as to be formed by conventional lithography.

Integrated circuit having pitch reduced patterns relative to photoithography features

Atomic layer deposition is enhanced using plasma. Plasma begins prior to flowing a second precursor into a chamber. The second precursor reacts with a first precursor to deposit a layer on a substrate. The layer may include at least one element from each of the first and second precursors. The layer may be TaN, and the precursors may be TaFand NH. The plasma may begin during purge gas flow between a pulse of the first precursor and a pulse of the second precursor. Thermal energy assists the reaction of the precursors to deposit the layer on the substrate. The thermal energy may be greater than generally accepted for ALD (e.g., more than 300 degrees Celsius).

Systems and methods for insitu post atomic layer deposition (ALD) destruction of active species are provided. ALD processes deposit multiple atomic layers on a substrate. Pre-cursor gases typically enter a reactor and react with the substrate resulting in a monolayer of atoms. After the remaining gas is purged from the reactor, a second pre-cursor gas enters the reactor and the process is repeated. The active species of some pre-cursor gases do not readily purge from the reactor, thus increasing purge time and decreasing throughput. A high-temperature surface placed in the reactor downstream from the substrate substantially destroys the active species insitu. Substantially destroying the active species allows the reactor to be readily purged, increasing throughput.

Insitu post atomic layer deposition destruction of active species

Differently-sized features of an integrated circuit are formed by etching a substrate using a mask which is formed by combining two separately formed patterns. Pitch multiplication is used to form the relatively small features of the first pattern and conventional photolithography used to form the relatively large features of the second pattern. Pitch multiplication is accomplished by patterning a photoresist and then etching that pattern into an amorphous carbon layer. Sidewall spacers are then formed on the sidewalls of the amorphous carbon. The amorphous carbon is removed, leaving behind the sidewall spacers, which define the first mask pattern. A bottom anti-reflective coating (BARC) is then deposited around the spacers to form a planar surface and a photoresist layer is formed over the BARC. The photoresist is next patterned by conventional photolithography to form the second pattern, which is then is transferred to the BARC. The combined pattern made out by the first pattern and the second pattern is transferred to an underlying amorphous silicon layer and the pattern is subjected to a carbon strip to remove BARC and photoresist material. The combined pattern is then transferred to the silicon oxide layer and then to an amorphous carbon mask layer. The combined mask pattern, having features of difference sizes, is then etched into the underlying substrate through the amorphous carbon hard mask layer.

Pitch reduced patterns relative to photolithography features

Methods of controlling critical dimensions of reduced-sized features during semiconductor fabrication through pitch multiplication are disclosed. Pitch multiplication is accomplished by patterning mask structures via conventional photoresist techniques and subsequently transferring the pattern to a sacrificial material. Spacer regions are then formed on the vertical surfaces of the transferred pattern following the deposition of a conformal material via atomic layer deposition. The spacer regions, and therefore the reduced features, are then transferred to a semiconductor substrate.

Method to deposit conformal low temperature SiO2

Pitch multiplication is performed using a two step process to deposit spacer material on mandrels. The precursors of the first step react minimally with the mandrels, forming a barrier layer against chemical reactions for the deposition process of the second step, which uses precursors more reactive with the mandrels. Where the mandrels are formed of amorphous carbon and the spacer material is silicon oxide, the silicon oxide is first deposited by a plasma enhanced deposition process and then by a thermal chemical vapor deposition process. Oxygen gas and plasma-enhanced tetraethylorthosilicate (TEOS) are used as reactants in the plasma enhanced process, while ozone and TEOS are used as reactants in the thermal chemical vapor deposition process. The oxygen gas is less reactive with the amorphous carbon than ozone, thereby minimizing deformation of the mandrels caused by oxidation of the amorphous carbon.

Multiple deposition for integration of spacers in pitch multiplication process

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Shuang Meng