Taiwan Semiconductor Manufacturing Comp. Ltd.

Shu-Wei Chung

Kuo-Feng Yu

Yen-Sen Wang

Chung-Hui Chen

Tung-Heng Hsieh

Shyue-Shyh Lin

Chia-Der Chang

Tsung-Hsin Yu

Min-Hsiung Chiang

Pin-Cheng Hsu

Chung-Yi Lin

Yung Feng Chang

Wan-Te Chen

Tzu-Ching Chang

Chih Hsiung Lin

Hao Wen Hsu

A semiconductor device includes a substrate. A first nanosheet structure and a second nanosheet structure are disposed on the substrate. Each of the first and second nanosheet structures have at least one nanosheet forming source/drain regions and a gate structure including a conductive gate contact. A first oxide structure is disposed on the substrate between the first and second nanosheet structures. A conductive terminal is disposed in or on the first oxide structure. The conductive terminal, the first oxide structure and the gate structure of the first nanosheet structure define a capacitor.

Capacitor in nanosheet

A method includes forming a seed layer on a semiconductor wafer, coating a photo resist on the seed layer, performing a photo lithography process to expose the photo resist, and developing the photo resist to form an opening in the photo resist. The seed layer is exposed, and the opening includes a first opening of a metal pad and a second opening of a metal line connected to the first opening. At a joining point of the first opening and the second opening, a third opening of a metal patch is formed, so that all angles of the opening and adjacent to the first opening are greater than 90 degrees. The method further includes plating the metal pad, the metal line, and the metal patch in the opening in the photo resist, removing the photo resist, and etching the seed layer to leave the metal pad, the metal line and the metal patch.

Integrated circuit features with obtuse angles and method of forming same

An analog standard cell is provided. An analog standard cell according to the present disclosure includes a first active region and a second active region extending along a first direction, and a plurality of conductive lines in a first metal layer over the first active region and the second active region. The plurality of conductive lines includes a first conductive line and a second conductive line disposed directly over the first active region, a third conductive line and a fourth conductive line disposed directly over the second active region, a middle conductive line disposed between the second conductive line and the third conductive line, a first power line spaced apart from the middle conductive line by the first conductive line and the second conductive line, and a second power line spaced apart from the middle conductive line by the third conductive line and the fourth conductive line.

Standard cell design

A semiconductor structure and method of forming the same are provided. The semiconductor structure has a conductive structure. The semiconductor structure includes a first conductive line, a second conductive line, a third conductive line and a conductive via. The first conductive line and the second conductive line are located in a first dielectric layer and extend along a first direction. The first conductive line and the second conductive line are spaced from each other by the first dielectric layer therebetween. The third conductive line is located in a second dielectric layer and extends along a second direction. The conductive via is vertically between the first conductive line and the third conductive line, and between the second conductive line and the third conductive line. The conductive via, in a vertical direction, is overlapped with a portion of the first dielectric layer that is laterally between the first conductive line and the second conductive line.

Semiconductor structure with via extending across adjacent conductive lines and method of forming the same

An integrated circuit (IC) device according to the present disclosure includes a substrate including a first surface and a second surface opposing the first surface, a redistribution layer disposed over the first surface and including a conductive feature, a passivation structure disposed over the redistribution layer, a metal-insulator-metal (MIM) capacitor embedded in the passivation structure, a dummy MIM feature embedded in the passivation structure and including an opening, a top contact pad over the passivation structure, a contact via extending between the conductive feature and the top contact pad, and a through via extending through the passivation structure and the substrate. The dummy MIM feature is spaced away from the MIM capacitor and the through via extends through the opening of the dummy MIM feature without contacting the dummy MIM feature.

Method for inserting dummy capacitor structures

Integrated circuit features with obtuse angles and method forming same

Some embodiments of the present disclosure provide a semiconductor device including a substrate and a gate structure on the substrate. A first well region of a first conductivity type is in the substrate, close to a first sidewall of the gate structure. A second well region of a second conductivity type is also in the substrate close to the second sidewall of the gate structure. A conductive region is disposed in the second well region. The conductive region can be an epitaxy region. A chemical composition inside the second well region between the conductive region and the gate structure is essentially homogeneous as a chemical composition throughout the second well region.

Semiconductor structure and manufacturing method thereof

A semiconductor device is provided which includes a semiconductor substrate, a gate structure formed on the substrate, sidewall spacers formed on each side of the gate structure, a source and a drain formed in the substrate on either side of the gate structure, the source and drain having a first type of conductivity, a lightly doped region formed in the substrate and aligned with a side of the gate structure, the lightly doped region having the first type of conductivity, and a barrier region formed in the substrate and adjacent the drain. The barrier region is formed by doping a dopant of a second type of conductivity different from the first type of conductivity.

High voltage device with reduced leakage

A device includes a first and a second HVMOS device, each includes a gate electrode over a semiconductor substrate, wherein the gate electrodes of the first and the second HVMOS devices have a first gate length and a second gate length, respectively, with the second gate length being greater than the first gate length. Each of the first and second HVMOS devices includes a first and a second well region of a p-type and an n-type, respectively, and a native region between and contacting the first and the second well regions. The first and the second well regions have higher impurity concentrations than the native region. The native region of the first HVMOS device and the native region of the second HVMOS device have a first native-region length and a second native-region length, respectively, wherein the second native-region length is greater than the first native-region length.

HVMOS devices and methods for forming the same

A method includes providing a substrate comprising a first device region and a second device region; forming an oxide cap over the substrate and in the first device region and the second device region; forming a first metal layer over the oxide cap, wherein the first metal layer has a first portion in the first device region and a second portion in the second device region; forming a mask to cover the second portion of the first metal layer, wherein the first portion of the first metal layer is exposed; removing the first portion of the first metal layer and the oxide cap from the first device region; removing the mask; and forming a second metal layer in the first device region and the second device region, wherein the second metal layer in the second device region is over the second portion of the first metal layer.

Method of fabricating a gate stack integration of complementary MOS device

A method of forming an integrated circuit structure includes providing a substrate comprising a first device region and a second device region; forming an oxide cap over the substrate and in the first device region and the second device region; forming a first metal layer over the oxide cap, wherein the first metal layer has a first portion in the first device region and a second portion in the second device region; forming a mask to cover the second portion of the first metal layer, wherein the first portion of the first metal layer is exposed; removing the first portion of the first metal layer and the oxide cap from the first device region; removing the mask; and forming a second metal layer in the first device region and the second device region, wherein the second metal layer in the second device region is over the second portion of the first metal layer.

Growing community of inventors

Taichung, Taiwan

Shu-Wei Chung