Taiwan Semiconductor Manufacturing Comp. Ltd.

Shu-Shen Yeh

Shin-Puu Jeng

Po-Yao Lin

Chin-Hua Wang

Yu-Sheng Lin

Ming-Chih Yew

Chia-Kuei Hsu

Po-Chen Lai

Che-Chia Yang

Shyue-Ter Leu

Kuang-Chun Lee

Feng-Cheng Hsu

Wen-Yi Lin

Chien-Sheng Chen

Hui-Chang Yu

Shuo-Mao Chen

Chien-Hung Chen

Chia-Hsiang Lin

Li-Ling Liao

Cheng-Yi Hong

Tsung-Yen Lee

Chih-Kung Huang

Chien Hung Chen

Tsung-Ming Yeh

Yu Chen Lee

Cheng-Lin Huang

Chien-Hung Zordius Chen

Kuo-Ching Hsu

Kai-Ming Ching

Han-Hsiang Huang

Yu-Min Cheng

Ya-Huei Lee

Hsiu-Mei Yu

Yu-Huan Chen

Yi-Hang Lin

Chien-Shen Chen

Shyue Ter Leu

Shin-Puu Zeng

Yu-Chen Lee

Yi Hang Lin

Chia Kuei Hsu

Chipta Priya Laksana

A method includes forming an interconnect component including a plurality of dielectric layers that include an organic dielectric material, and a plurality of redistribution lines extending into the plurality of dielectric layers. The method further includes bonding a first package component and a second package component to the interconnect component, encapsulating the first package component and the second package component in an encapsulant, and precutting the interconnect component using a blade to form a trench. The trench penetrates through the interconnect component, and partially extends into the encapsulant. The method further includes performing a singulation process to separate the first package component and the second package component into a first package and a second package, respectively.

Dicing process in packages comprising organic interposers

Semiconductor devices having improved under-bump metallization layouts and methods of forming the same are disclosed. In an embodiment, a semiconductor device includes an IC die; an interconnect structure coupled to the IC die and including a metallization pattern including a via portion extending through a dielectric layer; a second dielectric layer over the dielectric layer opposite the IC die; and a second metallization pattern coupled to the metallization pattern and including a line portion in the dielectric layer and a second via portion extending through the second dielectric layer; and a UBM over the second metallization pattern and the second dielectric layer, the UBM being coupled to the second metallization pattern, a centerline of the via portion and a second centerline of the second via portion being misaligned with a third centerline of the UBM, the centerline and the second centerline being on opposite sides of the third centerline.

Semiconductor package and method of manufacture

A semiconductor package includes a first die, a second die and a buffer layer. The first die and the second die are stacked on the first die. The buffer layer is disposed on a first sidewall of the second die, wherein a second sidewall opposite to the first sidewall of the second die is flush with a third sidewall of the first die.

Integrated fan-out package having stress release structure

Semiconductor devices and methods of manufacture which utilize lids in order to constrain thermal expansion during annealing are presented. In some embodiments lids are placed and attached on encapsulant and, in some embodiments, over first semiconductor dies. As such, when heat is applied, and the encapsulant attempts to expand, the lid will work to constrain the expansion, reducing the amount of stress that would otherwise accumulate within the encapsulant.

Semiconductor device and method of manufacture

A package includes a package substrate, the package substrate having a first side and a second side opposite to the first side, a package component bonded to the first side of the package substrate, a front-side warpage control structure attached to the first side of the package substrate, and a backside warpage control structure embedded in the package substrate from the second side of the package substrate. The front-side warpage control structure includes a first disconnected structure and a second disconnected structure laterally separated from each other by a gap. The backside warpage control structure includes a third disconnected structure and a fourth disconnected structure laterally separated from each other.

Integrated circuit package and method of forming same

A package structure is provided. The package structure includes a first conductive pad in a first insulating layer, a conductive via in a second insulating layer directly under the first conductive pad, and a first under bump metallurgy structure directly under the first conductive via. In a first horizontal direction, the conductive via is narrower than the first under bump metallurgy structure, and the first under bump metallurgy structure is narrower than the first conductive pad.

Package structure

A semiconductor structure includes: a substrate; a package attached to a first surface of the substrate, where the package includes: an interposer, where a first side of the interposer is bonded to the first surface of the substrate through first conductive bumps; dies attached to a second side of the interposer opposing the first side; and a molding material on the second side of the interposer around the dies; a plurality of thermal interface material (TIM) films on a first surface of the package distal from the substrate, where each of the TIM films is disposed directly over at least one respective die of the dies; and a heat-dissipation lid attached to the first surface of the substrate, where the package and the plurality of TIM films are disposed in an enclosed space between the heat-dissipation lid and the substrate, where the heat-dissipation lid contacts the plurality of TIM films.

High efficiency heat dissipation using discrete thermal interface material films

A chip package structure is provided. The chip package structure includes a wiring substrate. The chip package structure includes an interposer substrate over the wiring substrate. The interposer substrate includes a redistribution structure, a dielectric layer, a conductive via, and a plurality of first dummy vias, the dielectric layer is over the redistribution structure, the conductive via and the first dummy vias pass through the dielectric layer, the first dummy vias surround the conductive via, and the first dummy vias are electrically insulated from the wiring substrate. The chip package structure includes a chip structure over the interposer substrate. The chip structure is electrically connected to the conductive via, and the chip structure is electrically insulated from the first dummy vias.

Method for forming chip package structure

A semiconductor die package is provided. The semiconductor die package includes a semiconductor die and a package substrate supporting and electrically connected to the semiconductor die. The semiconductor die has a corner. The package substrate includes several conductive lines, and one of the conductive lines under the corner of the semiconductor die includes a first line segment and a second line segment connected to the first line segment. The first line segment is linear and extends in a first direction. The second line segment is non-linear and has a varying extension direction.

Semiconductor die package with conductive line crack prevention design

A chip package structure is provided. The chip package structure includes a wiring substrate. The chip package structure includes a first chip structure over the wiring substrate. The chip package structure includes a heat-spreading lid over the wiring substrate and covering the first chip structure. The heat-spreading lid includes a ring structure and a top plate, the ring structure surrounds the first chip structure, the top plate covers the ring structure and the first chip structure, and the first chip structure has a first sidewall and a second sidewall opposite to the first sidewall.

Chip package structure with lid

Provided is a package structure including a substrate, a stiffener ring, an eccentric die, a lid layer, and a buffer layer. The stiffener ring is disposed on the substrate. The stiffener ring has an inner perimeter to enclose an accommodation area. The eccentric die is disposed within the accommodation area on the substrate. The eccentric die is offset from a center of the accommodation area to close to a first side of the stiffener ring. The lid layer is disposed on the stiffener ring and overlays the eccentric die. The buffer layer is embedded in the lid layer between the first side of the stiffener ring and the eccentric die. The buffer layer has a thickness less than a thickness of the lid layer.

Package structure with buffer layer embedded in lid layer

Semiconductor packages and methods of fabricating semiconductor packages include a package substrate having a recess formed in a surface of the package substrate and at least one channel in a bottom surface of the recess. The recess may be configured to accommodate a semiconductor device located over a surface of an interposer that is bonded to the package substrate. Accordingly, a minimum gap distance may be maintained between the semiconductor device and the package substrate, which may ensure that sufficient underfill material may flow between the semiconductor device and the package substrate and within the at least one channel, thereby improving of the structural coupling between the interposer and the package substrate, and reducing the likelihood of package defects, such as delamination, cracking, and/or popcorn defects.

Semiconductor package with substrate recess and methods for forming the same

A multi-chip device includes a first material within a substrate. The first material has a first coefficient of thermal expansion different than a second coefficient of thermal expansion of the substrate. A first chip overlies a first portion of the first material and a first portion of the substrate. A second chip overlies a second portion of the first material and a second portion of the substrate. The first material is between the first portion of the substrate and the second portion of the substrate.

Multi-chip device and method of formation

A semiconductor structure includes a fan-out package comprising at least one semiconductor die, a redistribution structure comprising fan-out bonding pads, and a first underfill material portion, a packaging substrate comprising chip-side bonding pads, solder material portions bonded to the chip-side bonding pads and the fan-out bonding pads, a second underfill material portion laterally surrounding the solder material portions, and at least one cushioning film located on the packaging substrate and contacting the second underfill material portion and having a Young's modulus that is lower than a Young's modulus of the second underfill material portion.

Underfill cushion films for packaging substrates and methods of forming the same

A manufacturing method of a semiconductor package includes the following steps. A first semiconductor device is provided over a substrate, wherein the first semiconductor device is offset toward an edge of the substrate. A ring structure is attached to the substrate by a first adhesive layer, wherein the ring structure surrounds the first semiconductor device and comprises an overhang portion cantilevered over the edge of the substrate. A lid structure is attached to the ring structure by a second adhesive layer, wherein the lid structure covers the first semiconductor device and comprises an extending portion covering the overhang portion.

Growing community of inventors

Taoyuan, Taiwan

Shu-Shen Yeh