United Microelectronics Corp.

Elan Microelectronics Corporation

United Semiconductor Corp.

United Semiconductor Circuit Corp.

Shu-Jen Chen

Chih-Ching Hsu

Ruoh-Haw Chang

Kuen-Syh Tseng

Jiunn-Hsien Lin

Joe Ko

Ming-Shing Chen

Jy-Hwang Lin

Yong-fen Hsieh

Wei-Shiau Chen

William Lu

Chien-Chih Lin

Jacky Kuo

Chang Ou Yang

In control methods for a multi-function controller, which includes a sensor having a ring operation region, the position of an object on the sensor is detected for generating a position information, and the force applied to the sensor by the object is detected for generating a force information. When the sensor detects multiple successive position information, which indicate that the object is circling along the ring operation region, a rotation information may be generated additionally. The position information, the force information and the rotation information are used to perform operation in various functional modes.

Control methods for a multi-function controller

A multi-film capping layer having a cobalt layer, a barrier layer, and a stuffing layer is disclosed, wherein the barrier layer isolates the cobalt layer from the stuffing layer. The multi-film capping layer is formed on a gate transistor and applicable to a self-aligned silicide (salicide) process, so that a sheet resistance of the salicide layer on conductive regions of the gate transistor is significantly reduced. The stuffing layer further prevents entry of oxygen or moisture to the salicide layer, thus no cobalt oxide is formed when RTP is performed. Without formation of the cobalt oxide, the salicide process is free from the bridging issue and the filament issue.

Multi-film capping layer for a salicide process

A method for forming silicide on a semiconductor wafer. The semiconductor wafer includes a doped silicon layer on a predetermined area of the semiconductor wafer, a metal layer positioned on the doped silicon layer, and a barrier layer covering the metal layer. A first rapid thermal processing (RTP) step is performed to make portions of the metal layer react with silicon inside the doped silicon layer so as to form a transitional silicide. The barrier layer and the portions of the metal layer that have not reacted with silicon are then removed. A dielectric layer is formed on the transitional silicide. Finally, a second rapid thermal processing (RTP) step is performed to make the transitional silicide react with portions of the doped silicon layer so as to form the silicide.

Method for forming silicide

A method of fabricating a preserve layer. A top metallic layer is formed over the substrate. Portions of the metallic layer and the substrate are removed to form a trench. A conformal pad oxide layer is formed over the substrate. A conformal first nitride layer is formed on the pad oxide layer. A spin-on glass layer is formed on the first nitride layer to fill the trench. An etching back step is performed to remove a portion of the spin-on glass layer. The remaining spin-on glass layer fills the trench to the surface of the first nitride layer above the top metallic layer. An oxide layer is formed over the substrate. A second nitride layer is formed on the oxide layer. A preserve layer comprising the pad oxide layer, the first nitride layer, the oxide layer, and the second nitride layer is formed.

Method of fabricating preserve layer

A method of manufacturing an interconnect. A first conductive layer is formed on the wafer. Portions of the first conductive layer are removed to form a wire in the interior region and to expose the surface of the wafer in the edge region, simultaneously. An insulating layer is formed on the wire and the wafer. An opening is formed to penetrate through the insulating layer and exposes the wire. A second conductive layer is formed on the insulating layer and fills the opening.

Method of manufacturing interconnect

A method of manufacturing a salicide layer is described. A substrate having a memory region and a logic circuit region is provided, wherein the memory region comprises a first gate structure and a first source/drain region and the logic circuit region comprises a second gate structure and a second source/drain region. A first salicide layer is formed on the second gate structure and the second source/drain region in the logic circuit region. A dielectric layer is formed over the substrate. A portion of the dielectric layer is removed to expose the first gate structure and the first salicide layer above the second gate structure. A second salicide layer is formed on the first and the second gate structure.

Method of manufacturing salicide layer

The invention relates to a method for manufacturing of a titanium self-aligned silicide (Salicide). This process includes of forming a metal layer over the surfaces of the semiconductor substrate and the gate electrode. Then, a rapid thermal process is performed with three stages to form the salicide, for example, titanium silicide, at the interface between the titanium and silicon, namely on the surfaces of the gate electrode and source/drain region. The rapid thermal process with three stages includes using the first stage with the first temperature to form the early titanium silicide having the C49 phase. The temperature is raised to a second temperature and the RTA process is performed with nitrogen gases to transform the high resistance phase C49 of the titanium nitride into a low resistance phase C54 in the second stage. Then, the temperature is rapidly raised to a third temperature to transform the C49 phase into the C54 phase completely and to prevent the agglomeration phenomenon.

Method of manufacturing self-aligned silicide

The method of the present invention includes forming a MOS on a semiconductor substrate. Subsequently, a silicon-rich metal silicide layer is deposited on the MOS and substrate by using chemical vapor deposition to act as a silicon material source. Then, a thermal process is carried out to separate a portion of the silicon out of the metal silicide layer, thereby forming a silicon layer on top of the gate of the MOS, source/drain. The nest step is to remove the metal suicide layer. A self-aligned metal silicide layer is formed on the silicon layer.

Method to grow self-aligned silicon on a poly-gate, source and drain

A field effect transistor which is not susceptible to mask edge detects at its gate spacer oxides. The transistor is formed upon a semiconductor substrate through successive layering of a gate oxide, a gate electrode and a gate cap oxide. A pair of curved gate spacer oxides are then formed covering opposite edges of the stack of the gate oxide, the gate electrode and the gate cap oxide. The semiconductor substrate is then etched to provide a smooth topographic transition from the gate spacer oxides to the etched semiconductor surface. Source/drain electrodes are then implanted into the etched semiconductor substrate and annealed to yield the finished transistor. A second embodiment of the field effect transistor possesses a polysilicon gate. Alter removal of the gate cap oxide, a metal layer may be deposited and sintered upon the polysilicon gate and the source/drain electrodes. The metal salicide layers formed upon the electrodes of the transistor have limited susceptibility to parasitic current leakage.

Process of forming a field effect transistor without spacer mask edge

A method of fabricating salicide and self-aligned barrier simultaneously is disclosed. The initial steps include sputtering a metal stack (Ti--TiN--Ti) and forming a salicide layer by thermally reacting the metal stack and the wafer followed by a chemical etching which removes the unreacted portions of the metal stack. The portions of the metal stack on Si can react with Si to form a TiSi.sub.2 layer, thus forming TiSi.sub.2 --TiN--TiSi.sub.2. The TiSi.sub.2 layer over the TiN layer acts as a mask in the chemical etching and protects the TiN layer from been etched. The diffusion barrier layer is thus formed simultaneously within the fabricating of salicide.

Growing community of inventors

Hsinchu, Taiwan

Shu-Jen Chen