Mediatek Corporation

Shu-Hsuan Lin

Chia-Wei Wang

Shih-Huang Huang

Shu-Lin Lai

A sense amplifier circuit includes a single-ended sense amplifier and an isolation switch. The isolation switch is coupled between a bias node and a first line of a memory device, receives an output of the single-ended sense amplifier and selectively isolates the bias node and the first line in response to the output of the single-ended sense amplifier. The first line is coupled to a plurality of memory cells of the memory device.

Sense amplifier circuits

A memory device includes a first signal line; a memory cell array divided into a first area and a second area and having a plurality of first memory cells and second memory cells in the first area and second area, respectively. The plurality of first and second memory cells are coupled the first signal line, and each has a reference node. A first voltage adjustment circuit adjusts voltages at the reference nodes of the plurality of first memory cells, wherein the first voltage adjustments circuit includes: a first switch coupled between the reference nodes of the plurality of first memory cells and the ground, controlled by an address signal; and a first bias element coupled to the reference nodes of the plurality of first memory cells. A second voltage adjustment circuit adjusts voltages at the reference nodes of the plurality of second memory cells.

Memory devices and control methods thereof

A memory device is provided. The memory device includes a first signal line, a memory cell array, first and second voltage adjustment circuits. The memory cell array is divided into first and second areas and includes first memory cells in the first area and second memory cells in the second area. The first and second memory cells are coupled the first signal line. Each of the first and second memory cells has a reference node. The first voltage adjustment circuit adjusts voltages at the reference nodes of the first memory cells. The second voltage adjustment circuit adjusts voltages at the reference nodes of the second memory cells. The reference nodes of the first memory cells are coupled to a ground through the first voltage adjustment circuit. The reference nodes of the second memory cells are coupled to the ground through the second voltage adjustment circuit.

Growing community of inventors

Hsinchu, Taiwan

Shu-Hsuan Lin