Taiwan Semiconductor Manufacturing Comp. Ltd.

Shou-Yi Wang

Chien-Hsun Chen

Jiun Yi Wu

Jiun-Yi Wu

Chung-Shi Liu

Chen-Hua Douglas Yu

Tsung-Shu Lin

Chien-Hsun Lee

Ming-Yen Chiu

Hsueh-Lung Cheng

Po-Yao Lin

Ching-Hua Hsieh

Tsung-Ding Wang

Kuo-Chin Chang

Wen-Yi Lin

A package structure, and a RDL structure are provided. The package structure incudes a die and a RDL structure electrically connected to the die. The RDL structure includes a first redistribution layer, a second redistribution layer and a third redistribution layer. The first redistribution layer includes a first ground plate. The second redistribution layer includes a second ground plate and a signal trace. The signal trace is laterally spaced from the second ground plate. The third redistribution layer includes a third ground plate. The third redistribution layer and the first redistribution layer are disposed on opposite sides of the second redistribution layer. The signal trace is staggered with at least one of the first ground plate and the third ground plate in a direction perpendicular to a top surface of the signal trace.

Package structure, RDL structure comprising redistribution layer having ground plates and signal lines

A semiconductor package is provided. The semiconductor package includes: semiconductor dies, separated from one another, and including die I/Os at their active sides; and a redistribution structure, disposed at the active sides of the semiconductor dies and connected to the die I/Os, wherein the redistribution structure includes first and second routing layers sequentially arranged along a direction away from the die I/Os, the first routing layer includes a ground plane and first signal lines laterally surrounded by and isolated from the first ground plane, the first signal lines connect to the die I/Os and rout the die I/Os from a central region to a peripheral region of the redistribution structure, the second routing layer includes second signal lines and ground lines, and the second signal lines and the ground lines respectively extend from a location in the peripheral region to another location in the peripheral region through the central region.

Semiconductor package and manufacturing method thereof

In an embodiment, a device includes: a semiconductor device; and a redistribution structure including: a first dielectric layer; a first grounding feature on the first dielectric layer; a second grounding feature on the first dielectric layer; a first pair of transmission lines on the first dielectric layer, the first pair of transmission lines being laterally disposed between the first grounding feature and the second grounding feature, the first pair of transmission lines being electrically coupled to the semiconductor device; a second dielectric layer on the first grounding feature, the second grounding feature, and the first pair of transmission lines; and a third grounding feature extending laterally along and through the second dielectric layer, the third grounding feature being physically and electrically coupled to the first grounding feature and the second grounding feature, where the first pair of transmission lines extend continuously along a length of the third grounding feature.

Integrated circuit package and method

A package has a first semiconductor die, a second semiconductor die, a redistribution structure and a metallic bolstering pattern. The second semiconductor die is disposed beside the first semiconductor die and spaced apart from the first semiconductor die with a distance. The redistribution structure is disposed over the first semiconductor die and the second semiconductor die and is electrically connected with the first and second semiconductor dies. The metallic bolstering pattern is disposed between the redistribution structure and the first and second semiconductor dies. The metallic bolstering pattern is disposed on the redistribution structure and located over the first and second semiconductor dies, and the metallic bolstering pattern extends across the distance between the first and second semiconductor dies and extends beyond borders of the first and second semiconductor dies.

Package including metallic bolstering pattern and manufacturing method of the package

A method includes forming a device structure, the method including forming a first redistribution structure over and electrically connected to a semiconductor device, forming a molding material surrounding the first redistribution structure and the semiconductor device, forming a second redistribution structure over the molding material and the first redistribution structure, the second redistribution structure electrically connected to the first redistribution structure, attaching an interconnect structure to the second redistribution structure, the interconnect structure including a core substrate, the interconnect structure electrically connected to the second redistribution structure, forming an underfill material on sidewalls of the interconnect structure and between the second redistribution structure and the interconnect structure.

Semiconductor device and method of manufacture

A package structure, a RDL structure and method of forming the same are provided. The package structure includes a die structure, a RDL structure and a conductive terminal. The RDL structure is electrically connected to the die structure. The conductive terminal is electrically connected to the die structure through the RDL structure. The RDL structure includes a first redistribution layer and a second redistribution layer over the first redistribution layer. The first redistribution layer includes a ground plate. The second redistribution layer includes a signal line, and the signal line includes a signal via and a signal trace, the signal trace is electrically connected to the first redistribution layer through the signal via, and an overlapping area between the signal trace and the ground plate in a direction perpendicular to a bottom surface of the signal trace is less than an area of the bottom surface of the signal trace.

Package structure, RDL structure comprising redistribution layer having ground plates and signal lines and method of forming the same

A semiconductor package includes a semiconductor die and a connection structure. The semiconductor die is laterally encapsulated by an insulating encapsulant. The connection structure is disposed on the semiconductor die, the connection structure is electrically connected to the semiconductor die, and the connection structure includes at least one first via, first pad structures, second vias, a second pad structure and a conductive terminal. The at least one first via is disposed over and electrically connected to the semiconductor die. The first pad structures are disposed over the at least one first via, wherein the at least one first via contacts at least one of the first pad structures. The second vias are disposed over the first pad structures, wherein the second vias contact the first pad structures. The second pad structure is disposed over and contacts the second vias, wherein a vertical projection of each of first pad structures overlaps with a vertical projection of the second pad structure, and an overall area of the vertical projections of the first pad structures is smaller than an area of the vertical projection of the second pad structure. The conductive terminal is disposed over and connects with the second pad structure.

Semiconductor package for wafer level packaging and manufacturing method thereof

A semiconductor arrangement and method of formation are provided. The semiconductor arrangement includes a metal trace under at least a first dielectric layer and a second dielectric layer. The metal trace is connected to a ball connection by a first via in the first dielectric layer and second via in the second dielectric layer. The metal trace is connected to a test pad at a connection point, where the connection point is under the first dielectric layer. The metal trace under at least the first dielectric layer and the second dielectric layer has increased stability and decreased susceptibility to cracking in least one of the ball connection, the connection point, the first via or the second via as compared to a metal trace that is not under at least a first dielectric layer and a second dielectric layer.

Semiconductor arrangement and formation thereof

In a package structure, a stiffener ring is over and bonded to a top surface of a first package component. A second package component is over and bonded to the top surface of the first package component, and is encircled by the stiffener ring. A metal lid is over and bonded to the stiffener ring. The metal lid has a through-opening.

Growing community of inventors

Hsinchu, Taiwan

Shou-Yi Wang