Kabushiki Kaisha Toshiba

Toshiba Memory Corporation

Kioxia Corporation

Shosuke Fujii

Hidenori Miyagawa

Daisuke Matsushita

Masumi Saitoh

Takayuki Ishikawa

Kiwamu Sakuma

Akira Takashima

Reika Ichihara

Masahiro Kiyotoshi

Tsunehiro Ino

Yuichiro Mitani

Masao Shingu

Takashi Yamauchi

Haruka Kusai

Naoki Yasuda

Jun Fujiki

Koichi Muraoka

Yuuichi Kamimuta

Yasushi Nakasaki

Marina Yamaguchi

Riichiro Takaishi

Fumitaka Arai

Ichiro Mizushima

Yoshifumi Nishi

Hiroki Tanaka

Chika Tanaka

Harumi Seki

Haruka Sakuma

Shoichi Kabuyanagi

Takashi Haimoto

Li Zhang

Kazuhiko Yamamoto

Atsuhiro Kinoshita

Toshiyuki Sasaki

Yusuke Arayashiki

Kunifumi Suzuki

Kiyohito Nishihara

Daisuke Hagishima

Takuya Konno

Hideki Inokuma

Izumi Hirano

Hiromichi Kuriyama

Masato Koyama

Seiji Inumiya

A semiconductor memory device comprises: a substrate; a first semiconductor portion provided separated from the substrate in a first direction intersecting a surface of the substrate, the first semiconductor portion extending in a second direction intersecting the first direction; a first gate electrode extending in the first direction; a first insulating portion which is provided between the first semiconductor portion and the first gate electrode, includes hafnium (Hf) and oxygen (O), and includes an orthorhombic crystal as a crystal structure; a first conductive portion provided between the first semiconductor portion and the first insulating portion; and a second insulating portion provided between the first semiconductor portion and the first conductive portion. An area of a facing surface of the first conductive portion facing the first semiconductor portion is larger than an area of a facing surface of the first conductive portion facing the first gate electrode.

Semiconductor memory device incorporating hafnium oxide insulative portions

The semiconductor memory device of the embodiment includes a stacked body including interlayer insulating layers and gate electrode layers alternately stacked in a first direction; a semiconductor layer provided in the stacked body and extending in the first direction; a first insulating layer provided between the semiconductor layer and the gate electrode layers; conductive layers provided between the first insulating layer and the gate electrode layers; and second insulating layers provided between the conductive layers and the gate electrode layers and the second insulating layers containing ferroelectrics. Two of the conductive layers adjacent to each other in the first direction are separated by one of the interlayer insulating layers interposed between the two of the conductive layers, and a first thickness of one of the gate electrode layers in the first direction is smaller than a second thickness of one of the conductive layers in the first direction.

Semiconductor memory device

A semiconductor memory device includes: a substrate; a plurality of first semiconductor portions arranged in a first direction intersecting a surface of the substrate; a first gate electrode extending in the first direction, the first gate electrode facing the plurality of first semiconductor portions from a second direction intersecting the first direction; a first insulating portion provided between the first semiconductor portions and the first gate electrode; a first wiring separated from the first gate electrode in the first direction; a second semiconductor portion connected to one end in the first direction of the first gate electrode and to the first wiring; a second gate electrode facing the second semiconductor portion; and a second insulating portion provided between the second semiconductor portion and the second gate electrode.

A semiconductor memory device includes a first wiring extending in a first direction, a second wiring extending in a second direction, a variable resistance film provided between these, a third wiring extending in a third direction, a first semiconductor section connected to the first wiring and the third wiring, a first gate electrode facing the first semiconductor section, a contact connected to the second wiring, a fourth wiring further from the substrate than the contact is, a second semiconductor section connected to the contact and the fourth wiring, and a second gate electrode facing the second semiconductor section. The first semiconductor section, the first gate electrode, the second semiconductor section, and the second gate electrode respectively include a portion included in a cross section extending in the second direction and the third direction.

According to one embodiment, a memory element includes a first layer, a second layer, and a third layer. The first layer is conductive. The second layer is conductive. The third layer includes hafnium oxide and is provided between the first layer and the second layer. The first layer includes a first region, a second region, and a third region. The first region includes a first element and a first metallic element. The first element is selected from a group consisting of carbon and nitrogen. The second region includes a second metallic element and is provided between the first region and the third layer. The third region includes titanium oxide and is provided between the second region and the third layer.

Memory element

According to one embodiment, a memory device includes a first conductive layer, a second conductive layer, a first insulating layer and a first layer. The first conductive layer includes a first metal capable of forming a compound with silicon. The second conductive layer includes at least one selected from a group consisting of tungsten, molybdenum, platinum, tungsten nitride, molybdenum nitride, and titanium nitride. The first insulating layer is provided between the first conductive layer and the second conductive layer. The first layer is provided between the first insulating layer and the second conductive layer. The first layer includes silicon.

Memory device

According to one embodiment, a nonvolatile memory device includes a first conductive layer, a second conductive layer, and an intermediate layer. The first conductive layer includes a first element. The first element includes a at least one selected from the group consisting of Ag, Cu, Ni, Co, Ti, Al, and Au. The intermediate layer is provided between the first conductive layer and the second conductive layer. The intermediate layer includes an oxide. The oxide includes a second element and a third element. The second element includes at least one second element being selected from the group consisting of Ti, Ta, Hf, W, Mg, Al, and Zr. The third element is different from the second element and includes at least one selected from the group consisting of Si, Ge, Hf, Al, Ta, W, Zr, Ti, and Mg.

Nonvolatile memory device

A semiconductor device according to an embodiment includes a first conductive layer, a second conductive layer, and a ferroelectric layer including hafnium oxide provided between the first conductive layer and the second conductive layer, a sum of hafnium (Hf) and oxygen (O) in the hafnium oxide being 98 atomic percent or more.

Semiconductor device, manufacturing method for semiconductor device, and ferroelectric layer

According to one embodiment, a semiconductor memory device includes a plurality of first wirings, second wirings, a plurality of memory cells, selection gate transistors, and a third wiring. The first wirings are disposed in a first direction along a surface of a substrate and in a second direction intersecting with the surface of the substrate. The selection gate transistors are connected to respective one ends of the second wirings. The third wiring is connected in common to one end of the selection gate transistors. The selection gate transistor includes first to third semiconductor layers laminated on the third wiring and a gate electrode. The gate electrode is opposed to the second semiconductor layer in the first direction. The second semiconductor layer has a length in the first direction smaller than lengths of the first semiconductor layer and the third semiconductor layer in the first direction.

Semiconductor memory device, semiconductor device, and method for manufacturing the same

According to one embodiment, a memory device includes a first electrode, a second electrode, a first layer, and a second layer. The first electrode includes a first element. The first layer is provided between the first electrode and the second electrode. The first layer includes at least one of an insulator or a first semiconductor. The second layer is provided between the first layer and the second electrode. The second layer includes a first region and a second region. The second region is provided between the first region and the second electrode. The second region includes a second element. A standard electrode potential of the second element is lower than a standard electrode potential of the first element. A concentration of nitrogen in the first region is higher than a concentration of nitrogen in the second region.

According to one embodiment, a memory device includes a first layer, a second layer, and a third layer provided between the first layer and the second layer. The first layer includes first interconnections and a first insulating portion. The first interconnections extend in a first direction. The first insulating portion is provided between the first interconnections. The second layer includes a plurality of second interconnections and a second insulating portion. The second interconnections extend in a second direction crossing the first direction. The second insulating portion is provided between the second interconnections. The third layer includes a ferroelectric portion and a paraelectric portion. The ferroelectric portion and the paraelectric portion include hafnium oxide.

Memory device including a layer including hafnium oxide and method for manufacturing the same

According to one embodiment, a semiconductor memory device includes a semiconductor layer, a plurality of conductive layers, a plurality of insulating layers, an intermediate layer, and a controller. The conductive layers and the insulating layers are alternately provided. The intermediate layer is provided between the plurality of conductive layers and the semiconductor layer. The controller is configured to perform first and second operations. In first operation, the controller applies a first voltage to the semiconductor layer, applies a second voltage higher than the first voltage to a first conductive layer, and applies a third voltage to other conductive layers. In the second operation, the controller applies a fourth voltage to the semiconductor layer, applies a fifth voltage to the first conductive layer, and applies a sixth voltage to the other conductive layers.

3D non-volatile memory array utilizing metal ion source

According to one embodiment, a resistance-change memory includes a memory cell and a control circuit. The memory cell comprises first and second electrodes, and a variable resistance layer disposed between the first electrode and the second electrode. The control circuit applies a voltage between the first electrode and the second electrode to perform writing, erasing, and reading. During the writing, the control circuit applies a first voltage pulse between the first electrode and the second electrode, and then applies a second voltage pulse different in polarity from the first voltage pulse after applying the first voltage pulse.

Resistance-change memory operating with read pulses of opposite polarity

According to one embodiment, a nonvolatile resistance change element includes a first electrode, a second electrode, a semiconductor layer and a first layer. The first electrode includes at least one of Ag, Ni, Co, Al, Zn, Ti, and Cu. The semiconductor layer is sandwiched between the first and second electrodes. The first layer is provided between the second electrode and the semiconductor layer and contains an element included in the semiconductor layer and at least one of Ag, Ni, and Co.

Nonvolatile resistance change element

According to one embodiment, a nonvolatile resistance change element includes a first electrode, a second electrode and a first layer. The first electrode includes a metal element. The second electrode includes an n-type semiconductor. The first layer is formed between the first electrode and the second electrode and includes a semiconductor element. The first layer includes a conductor portion made of the metal element. The conductor portion and the second electrode are spaced apart.

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Kuwana, Japan

Shosuke Fujii