Texas Instruments Corporation

Shoji Wada

Hiroshi Yamasaki

Yoshikazu Kondo

Masahiro Iwamoto

Jungwoo Joh

Chang Soo Suh

Dong Seup Lee

Karen Hildegard Ralston Kirmse

A semiconductor device includes a gallium nitride based low threshold depletion mode transistor (GaN FET) with a threshold potential between −10 volts and −0.5 volts. The GaN FET has a channel layer of III-N semiconductor material including gallium and nitrogen that supports a two-dimensional electron gas (2DEG). The GaN FET has a barrier layer of III-N semiconductor material including aluminum and nitrogen over the channel layer. The GaN FET further has a p-type gate of III-N semiconductor material including gallium and nitrogen. A bottom surface of the gate, adjacent to the barrier layer, does not extend past a top surface of the barrier layer, located opposite from the channel layer. The GaN FET is free of a dielectric layer between the gate and the barrier layer.

Normally-on gallium nitride based transistor with p-type gate

Metal contact openings are etched in the barrier layer of a group III-N HEMT with a first gas combination that etches down into the barrier layer, and a second gas combination that etches further down into the barrier layer to a depth that lies above the top surface of a channel layer that touches and lies below the barrier layer.

Method of forming metal contacts in the barrier layer of a group III-N HEMT

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Plano, TX, United States of America

Shoji Wada