Applied Materials, Inc.

Shiyu Yue

Wei Lei

Rongjun Wang

Yu Lei

Yi Xu

Aixi Zhang

Xingyao Gao

Yixiong Yang

Sahil Patel

Zhimin Qi

Ju Hyun Oh

Dien-Yeh Wu

Adolph Miller Allen

Xiangjin Xie

Xiaodong Wang

Kevin Kashefi

Tsung-Han Yang

Cong Trinh

Shirish A Pethe

Aravind Kamath

Anthony Chih-Tung Chan

Mukund Sundararajan

Chih-Hsun Hsu

Jiajie Cen

Geraldine M Vasquez

Da He

Borui Xia

Abulaiti Hairisha

Embodiments of methods and associated apparatus for filling a feature in a substrate are provided herein. In some embodiments, a method of depositing tungsten in features of a substrate includes: depositing a seed layer consisting essentially of tungsten in the features via a physical vapor deposition (PVD) process; and depositing a bulk layer consisting essentially of tungsten in the features via a chemical vapor deposition (CVD) process to fill the features such that the deposition of the bulk layer is selective to within the features as compared to a field region of the substrate, wherein the CVD process is performed by flowing hydrogen gas (H) at a first flow rate and a tungsten precursor at a second flow rate, and wherein the first flow rate is less than the second flow rate.

Self field-suppression CVD tungsten (W) fill on PVD W liner

A method of pre-cleaning in a semiconductor structure includes performing a plasma pre-treatment process to remove impurities from a surface of a semiconductor structure comprising a metal layer and a dielectric layer, performing a selective etch process to remove molybdenum oxide from a surface of the metal layer, the selective etch process comprising soaking the semiconductor structure in a precursor including molybdenum chloride (MoCl, MoCl) at a temperature of between 250° C. and 350° C., and performing a post-treatment process to remove chlorine residues and by-products of the selective etch process on the surface of the semiconductor structure.

Metal oxide preclean for bottom-up gapfill in MEOL and BEOL

A method of selective metal removal via gradient oxidation for a gap-fill includes performing process cycles, each process cycle including placing a wafer having a semiconductor structure thereon into a first processing station, the semiconductor structure including a dielectric layer patterned with a feature formed therein and a seed layer formed on sidewalls and a bottom surface of the feature and a top surface of the dielectric layer, performing a reduction process on the wafer in the first processing station, performing a gradient oxidation process on the wafer in the second processing station, performing a gradient etch process on the wafer in the third processing station, and performing the gradient etch process on the wafer in the fourth processing station, wherein the first, second, third, and fourth processing stations are located in an interior volume of a processing chamber.

One chamber multi-station selective metal removal

Magnet assemblies comprising a housing with a top plate each comprising aligned openings are described. The housing has a bottom ring and an annular wall with a plurality of openings formed in the bottom ring. The top plate is on the housing and has a plurality of openings aligned with the plurality of openings in the bottom ring of the housing. The magnet assembly may also include a non-conducting base plate and/or a conductive cover plate. Methods for using the magnet assembly and magnetic field tuning are also described.

Top magnets for decreased non-uniformity in PVD

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Santa Clara, CA, United States of America

Shiyu Yue