Applied Materials, Inc.

Omnivision Technologies, Inc.

Varian Semiconductor Equipment Associates, Inc.

Shiyu Sun

Naomi Yoshida

Nam Sung Kim

Bingxi Sun Wood

Benjamin Colombeau

Michael Patrick Chudzik

Theresa Kramer Guarini

Sung Won Jun

Vanessa Pena

Gang Chen

Errol Antonio C Sanchez

Sheng-Chin Kung

Miao Jin

Srinivas D Nemani

Wei Liu

Christopher Sean Olsen

Johanes F Swenberg

Keith Tatseun Wong

Hans-Joachim Ludwig Gossmann

Jacob Newman

Yuanwei Zheng

Jing Tang

Lin Dong

Tze Wing Poon

Udayan Ganguly

Sunderraj Thirupapuliyur

Vicky U Nguyen

Ellie Y Yieh

Duli Mao

Mikhail Korolik

Sean S Kang

Yihwan Kim

Hui Zang

Kurtis Leschkies

Bill Phan

Swaminathan T Srinivasan

Qin Wang

Raymond Hoiman Hung

Sing-Chung Hu

Yoshitaka Yokota

Adam Brand

Tatsuya E Sato

John O Dukovic

Dimitri R Kioussis

Myungsun Kim

Chih-Yang Chang

Chi-Nung Ni

Namsung Kim

Cynthia Sun Yee Lee

Chiao-Ti Huang

Gaetano Santoro

Swaminathar Srinivasan

Yoshita Yokota

Armin Yazdani

Image sensors, isolation structures, and techniques of fabrication are provided. An image sensor includes a source of electromagnetic radiation disposed on a substrate, a pixel array disposed on the substrate and thermally coupled with source of electromagnetic radiation, and an isolation structure disposed on the substrate between the source of electromagnetic radiation and the pixel array. The isolation structure can define a first reflective surface oriented on a first bias relative to a lateral axis of the pixel array and a second reflective surface oriented on a second bias relative to the lateral axis. The isolation structure can be configured to attenuate residual electromagnetic radiation reaching a proximal region of the pixel array by pairing a first reflection and a second reflection of the electromagnetic radiation by the first reflective surface and the second reflective surface.

Image sensor diagonal isolation structures

A pixel cell is formed on a semiconductor substrate having a front surface. The pixel cell includes a photodiode, a floating diffusion region, and a transfer gate. The photodiode is disposed in the semiconductor substrate. The floating diffusion region includes a first doped region disposed in the semiconductor substrate, wherein the first doped region extends from the front surface to a first junction depth in the semiconductor substrate. The transfer gate is configured to selectively couple the photodiode to the floating diffusion region controlling charge transfer between the photodiode and the floating diffusion region. The transfer gate includes a planar gate disposed on the front surface of the semiconductor substrate and a pair of vertical gate electrodes. Each vertical gate electrode extending a gate depth from the planar gate into the semiconductor substrate. The first junction depth is greater than the gate depth.

Pixel cell having anti-blooming structure and image sensor

An image sensor includes a semiconductor substrate and a multilayer film. The semiconductor substrate includes a photodiode and a back surface having a recessed region that surrounds the photodiode. The multilayer film is on, and conformal to, the recessed region, and includes N layer-groups of adjacent high-κ material layers. Each pair of adjacent high-κ material layers of a same layer-group of the N layer-groups includes (i) an outer-layer having an outer fixed-charge density and (ii) an inner-layer, located between the outer-layer and the recessed region, that has an inner fixed-charge density. Each of the outer and inner fixed-charge density is negative. The inner fixed-charge density is more negative than the outer fixed-charge density.

Passivation-enhanced image sensor and surface-passivation method

Embodiments provide methods for forming nanowire structures, such as, for example, horizontal gate-all-around (hGAA) structures. In one embodiment, a method includes selectively etching material from a stack disposed on a material layer located on a substrate with a plasma to create recesses on each of first and second sides of the stack and depositing a dielectric material on the first and second sides. The stack includes repeating pairs of first and second layers. The method also includes removing the dielectric material from the first and second sides, where the dielectric material remains in the recesses of the first and second sides, and selectively depositing a stressor layer on regions of the first and second sides which are unprotected by the dielectric material to form gaps between the stressor layer and the dielectric material remaining in the recesses of the first and second sides.

Horizontal gate-all-around device nanowire air gap spacer formation

A method for forming a deep trench isolation structure for a CMOS image sensor includes providing a trench that extends from a first side toward a second side of a semiconductor substrate. The trench has an opening on the first side and a bottom and sides. A conformal layer of B-doped oxide is deposited on the bottom and sides of the trench and is less than half a width of the trench leaving a depthwise recess in the trench. A second material is deposited on the conformal layer of B-doped oxide in the trench filling the recess in the trench to the first side. The conformal layer of B-doped oxide is annealed driving boron from the conformal layer of B-doped oxide to the semiconductor substrate forming a B-doped region as a passivation layer juxtaposed next to the conformal layer of B-doped oxide having negative fixed charges.

Method for passivating full front-side deep trench isolation structure

An image sensor with passivated full deep-trench isolation includes a semiconductor substrate, the substrate including a plurality of sidewalls that form a plurality of trenches that separates pixels of a pixel array, and a passivation layer lining the plurality of sidewall surfaces and the back surface of the semiconductor substrate. A method for forming an image sensor with passivated full deep-trench isolation includes forming trenches in a semiconductor substrate, filling the trenches with a sacrificial material, forming a plurality of photodiode regions, forming a circuit layer, thinning the semiconductor substrate, and removing the sacrificial material. A method for reducing noise in an image sensor includes removing material from a semiconductor substrate to form a plurality of trenches that extend from a front surface toward a back surface, and depositing a dielectric material onto the back surface and into the plurality of trenches through a back opening of each trench.

Semiconductor substrate with passivated full deep-trench isolation and associated methods of manufacture

Embodiments provide apparatuses and methods for forming nanowire structures with desired materials horizontal gate-all-around (hGAA) structures field effect transistor (FET) for semiconductor chips. In one embodiments, a nanowire structure is provided and includes a stack containing repeating pairs of a first layer and a second layer and having a first side and a second side opposite from the first side, a gate structure surrounding the stack, a source layer adjacent to the first side, and a drain layer adjacent to the second side. The stack also contains one or more gaps disposed between the source layer and the second layer and having a dielectric constant value of about 1 and one or more gaps disposed between the drain layer and the second layer and having a dielectric constant value of about 1.

Horizontal gate all around device nanowire air gap spacer formation

A method of routing electrical connections in a wafer-on-wafer structure comprises, bonding a metal bonding pad of a first wafer to a metal bonding pad of a second wafer; bonding first wafer to the second wafer with a material different from the metal bonding pads; forming metal interconnect structures connecting the metal bonding pad of the first wafer to a first device disposed within a first and second side of the first wafer; and forming metal interconnect structures connecting the metal bonding pad of the second wafer to a second and third devices disposed within the second wafer, to connect the first device to the second and third devices through the metal bonding pads, wherein the electrical connections of the devices between the first and second wafers do not have a through-via that passes completely through the first or the second wafer.

Metal routing in image sensor using hybrid bonding

Embodiments described herein generally relate to methods and device structures for horizontal gate all around (hGAA) isolation and fin field effect transistor (FinFET) isolation. A superlattice structure comprising different materials arranged in an alternatingly stacked formation may be formed on a substrate. In one embodiment, at least one of the layers of the superlattice structure may be oxidized to form a buried oxide layer adjacent the substrate.

Horizontal gate all around and FinFET device isolation

A method for manufacturing an image sensor includes, for each of a plurality of photosensitive pixels of the image sensor, forming a trench in a semiconductor substrate of the image sensor, and depositing temporary transfer gate material in and above the trench. The method further includes, after the step of depositing temporary transfer gate material, high-temperature annealing at least a portion of the semiconductor substrate. In addition, the method includes, after the step of high-temperature annealing, (a) removing the temporary transfer gate material, thereby reopening the trench, (b) depositing a passivation lining, having a high-k dielectric, in the reopened trench, and (c) depositing metal on the high-k dielectric passivation lining to form a metal vertical transfer gate in the trench and extending above the trench.

Metal vertical transfer gate with high-k dielectric passivation lining

The present disclosure provide methods for forming nanowire structures with desired materials horizontal gate-all-around (hGAA) structures field effect transistor (FET) for semiconductor chips. In one example, a method of forming nanowire structures on a substrate includes forming a multi-material layer on a bottom structure on a substrate, wherein the multi-material layer includes repeating pairs of a first layer and a second layer, selectively removing the second layer from the multi-material layer from the substrate, and selectively oxidizing the bottom structure on the substrate after removing the second layer from the multi-material layer.

Methods for forming device isolation for semiconductor applications

Embodiments described herein generally relate to methods and device structures for horizontal gate all around (hGAA) isolation and fin field effect transistor (FinFET) isolation. A superlattice structure comprising different materials arranged in an alternatingly stacked formation may be formed on a substrate. In one embodiment, at least one of the layers of the superlattice structure is oxidized by a high pressure oxidation process to form a buried oxide layer adjacent the substrate.

Selective oxidation for 3D device isolation

The present disclosure provides an apparatus and methods for forming nanowire structures with desired materials horizontal gate-all-around (hGAA) structures field effect transistor (FET) for semiconductor chips. In one example, a method of forming nanowire structures includes depositing a dielectric material on a first side and a second side of a stack. The stack may include repeating pairs of a first layer and a second layer. The first side is opposite the second side and the first side and the second side have one or more recesses formed therein. The method includes removing the dielectric material from the first side and the second side of the stack. The dielectric material remains in the one or more recesses. The method includes the deposition of a stressor layer and the formation of one or more side gaps between the stressor layer and the first side and the second side of the stack.

Embodiments described herein generally relate to methods and apparatus for horizontal gate all around (hGAA) isolation. A superlattice structure comprising different materials arranged in an alternatingly stacked formation may be formed on a substrate. The different materials may be silicon containing materials and one or more III/V materials. In one embodiment, at least one of the layers of the superlattice structure may be oxidized to form a buried oxide layer adjacent the substrate.

Horizontal gate all around device isolation

Growing community of inventors

Santa Clara, CA, United States of America

Shiyu Sun