Intel Corporation

Ampere Computing LLC

Shivnandan D Kaushik

Bryant E Bigbee

James B Crossland

Hong Wang

Gautham N Chinya

Baiju V Patel

Prashant Sethi

Xiang Chris Zou

Richard A Hankins

Per H Hammarlund

John Thomas Shen

Anil Aggarwal

Mohan J Kumar

James Paul Held

John L Reid

Jason W Brandt

Linda J Rankin

John P Shen

Xinmin Tian

David J O'Shea

Scott Dion Rodgers

Keshavan K Tiruvallur

Rajesh S Parthasarathy

Trung Am Diep

Luke Hood

Alon Naveh

Jeffrey R Wilcox

Lance E Hacking

Sanjiv M Shah

Ryan N Rakvic

David I Poisner

Edward Thomas Grochowski

Stephen H Gunther

Milind Baburao Girkar

Quinn Able Jacobson

Devadatta V Bodas

Sridhar Muthrasanallur

Andrew J Fish

Asit K Mallick

Suresh K Marisetty

Nagi Aboulenein

Paul M Petersen

John William Horigan

Siva Ramakrishnan

Harb Abdulhamid

Bernard Lint

Ed Grochowski

Yogesh Bansal

Sebastien Hily

Vanshidhar Konda

Sachhidh Kannan

Ping Sager

Anil Aggawal

Koichi Yamada

Dion Rodgers

Dean A Mulla

Ashish Gupta

Lily Pao Looi

Douglas M Carmean

Kushagra V Vaid

Jose Andy Vargas

Chris J Newburn

Raymond Scott Tetrick

Frank Binns

Deep K Buch

Mani Ayyar

Keith Robert Pflederer

Massimo Sutera

James Charles Abel

David K Poulsen

Ling Cen

Todd Aldridge Dutton

Eshwari Prasad Komarla

Matthew Robert Erler

Scott D Brenden

Donald Scott Phillips

Kenneth S Reneris

Stanley Steven Kulick

David O'SHEA

Disclosed are techniques for memory resource control using Memory System Resource Partitioning and Monitoring (MPAM). In an aspect, a method of memory-system resource usage monitoring on a processing unit may include attaching a partition identifier from a set of partition identifiers to each memory access request of a plurality of memory access requests on an interconnect. The method may also include interleaving each memory access request of the plurality of memory access requests to a set of memory system components. The method may also include determining a first bandwidth associated with a first memory system component of the set of memory system components. The method may also include applying the first bandwidth associated with the first memory system component to one or more other memory system components of the set of memory system components based at least in part on the interleaving each memory access request.

Techniques for memory resource control using memory resource partitioning and monitoring

Address range memory mirroring in a computer system, and related methods and computer-readable media. The computer system includes one or more memory mirror agents that are each configured to be programmed to mirror write data of a write request to a memory address mapped to the memory mirror agent. The memory mirror agent is configured to mirror write data to a redundant memory space in memory if the write memory address is within a programmed memory space to be mirrored by the memory mirror agent. The memory mirror agent can be programmed to perform memory mirroring based on specific address ranges to provide flexibility in controlling and changing the exact memory space of the memory system to be mirrored. If an error is detected in read data in response to a memory read request, the memory mirror agent can retrieve the stored redundant data to maintain data integrity.

Address-range memory mirroring in a computer system, and related methods

Disclosed are techniques for performing a low-impact firmware update to a first microcontroller. In an aspect, a security entity communicatively coupled to the first microcontroller receives an update to firmware of the first microcontroller, authenticates the update to the firmware of the first microcontroller to prevent a security-related rollback, offloads system management tasks and interrupt handling from the first microcontroller to at least a second microcontroller communicatively coupled to the first microcontroller, coordinates installation of the update to the firmware of the first microcontroller without taking processing cycles from host software, and restores, to the first microcontroller, system management states occurring after the system management tasks and interrupt handling are offloaded from the first microcontroller.

Low-impact firmware update

Disclosed are techniques for management of multiple processor cores in a multi-core system-on-chip (SoC). In an implementation, the SoC may configure each processor core in a first subset of processor cores as a management controller for performing system management functions for processor cores not in the first subset, the first subset comprising at least one processor core from the plurality of processor cores. System management functions are handled by the processor cores in the first subset, while operating system functions are handled by the processor cores not in the first subset. In an implementation, the number of processor cores to be included in the first subset (which may be zero if it is desired that the SoC may operate in legacy mode), may be controlled at boot time according to a boot setting.

System-on-chip management controller

In an embodiment, a method is provided. The method includes managing user-level threads on a first instruction sequencer in response to executing user-level instructions on a second instruction sequencer that is under control of an application level program. A first user-level thread is run on the second instruction sequencer and contains one or more user level instructions. A first user level instruction has at least 1) a field that makes reference to one or more instruction sequencers or 2) implicitly references with a pointer to code that specifically addresses one or more instruction sequencers when the code is executed.

Mechanism for instruction set based thread execution on a plurality of instruction sequencers

Mechanism for instruction set based thread execution of a plurality of instruction sequencers

Embodiments of the invention provide a method of creating, based on an operating-system-scheduled thread running on an operating-system-visible sequencer and using an instruction set extension, a persistent user-level thread to run on an operating-system-sequestered sequencer independently of context switch activities on the operating-system-scheduled thread. The operating-system-scheduled thread and the persistent user-level thread may share a common virtual address space. Embodiments of the invention may also provide a method of causing a service thread running on an additional operating-system-visible sequencer to provide operating system services to the persistent user-level thread. Embodiments of the invention may further provide apparatus, system, and machine-readable medium thereof.

Apparatus, system, and method for persistent user-level thread

Method, apparatus and system embodiments to schedule OS-independent 'shreds' without intervention of an operating system. For at least one embodiment, the shred is scheduled for execution by a scheduler routine rather than the operating system. A scheduler routine may run on each enabled sequencer. The schedulers may retrieve shred descriptors from a queue system. The sequencer associated with the scheduler may then execute the shred described by the descriptor. Other embodiments are also described and claimed.

Mechanism to schedule threads on OS-sequestered sequencers without operating system intervention

A technique to enable efficient interrupt communication within a computer system. In one embodiment, an advanced programmable interrupt controller (APIC) is interfaced via a set of bits within an APIC interface register using various interface instructions or operations, without using memory-mapped input/output (MMIO).

Technique for communicating interrupts in a computer system

According to an embodiment of the invention, a method and apparatus for inter-processor interrupts in a multi-processor system are described. An embodiment comprises writing an inter-processor interrupt request to a first memory location; monitoring the first memory location; detecting the inter-processor interrupt request in the first memory location; calling a function for the inter-processor interrupt request; and performing the function for the inter-processor interrupt request.

Inter-processor interrupts

A technique to monitor software thread performance and update software that issues or uses the thread(s) to reduce performance-inhibiting events. At least one embodiment of the invention uses hardware and/or software timers or counters to monitor various events associated with executing user-level threads and report these events back to a user-level software program, which can use the information to avoid or at least reduce performance-inhibiting events associated with the user-level threads.

Mechanism for monitoring instruction set based thread execution on a plurality of instruction sequencers

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Portland, OR, United States of America

Shivnandan D Kaushik