Advanced Semiconductor Engineering, Inc.

Shiun Jaw Hsien

Yung I Yeh

Shu Jung Ma

A BGA semiconductor package comprises a chip mounted on the central region of the upper surface on the substrate. The substrate includes an upper surface, a lower surface, a ground plate disposed under the upper surface, and at least one power plate disposed between the ground plate and the lower surface. A ground ring surrounds the periphery of the chip and possesses a first set of serrated portions extending toward the outer edge of the substrate. A first power ring surrounds the ground ring and possesses a second set of serrated portions extending among the first set of serrated portions of the ground ring, such that the extending portions of the first and second sets of serrated rings interlace coincidentally with each other and the wire bonding distances from the bonding pads of chip surface to the extending portions of the first and the second serrated rings are comparable. According to another aspect of the present invention, a plurality of power vias are dispersedly distributed in the power ring to electrically connect the power ring to the power plate, wherein at least two power vias are coupled together. The coupled power vias can reduce the damage to the wholeness of ground plate thus enables the best electrical performance of the ground plate.

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Kaohsiung, Taiwan

Shiun Jaw Hsien