Sandisk Technologies Inc.

Shinsuke Yada

Hiroyuki Ogawa

Masanori Tsutsumi

Yanli Zhang

Sayako Nagamine

Johann Alsmeier

Masatoshi Nishikawa

Akio Nishida

Kiyohiko Sakakibara

Mitsuteru Mushiga

Teruo Okina

Ryoichi Honma

Shigehiro Fujino

Kazuki Isozumi

Akihisa Sai

Christopher John Petti

James K Kai

Jiahui Yuan

Huai-Yuan Tseng

Tong Zhang

Yu-Chung Lien

Zhixin Cui

Abhijith Prakash

Fumitaka Amano

Naohiro Hosoda

Yuji Fukano

Junichi Ariyoshi

Masanori Terahara

Tomoyuki Obu

Ryousuke Itou

Syo Fukata

Xiaolong Hu

Masato Miyamoto

Keyur Payak

Kensuke Ishikawa

Motoki Kawasaki

Yusuke Osawa

Hiroyuki Kamiya

Hajime Kimura

Takashi Kashimura

Shogo Tomita

Motoo Ohaga

Naoki Ihata

Takashi Orimoto

Ryo Yoshimoto

A three-dimensional memory device includes primary source side select gate electrodes located between word lines and bottom source side select gate electrodes. The primary source side select gate electrodes are laterally separated in each memory block, while the word lines and the bottom source side select gate electrodes are not laterally separated in each memory block.

Three-dimensional memory device with laterally separated source select electrodes and methods of forming the same

To address neighbor select gate interference between neighboring NAND block sub-divisions when one sub-division is program selected and its neighbor is un-selected, a biasing scheme for the GIDL select gates is introduced to reduce such disturbs. In a three-dimensional NAND memory with a sub-division structure and with two drain side GIDL select gate layers, when a sub-division is program selected and its neighboring sub-division is un-selected, the upper of the two drain side GIDL select gate layers is biased to a first voltage for all of the sub-divisions, while for the lower drain side GIDL select gate layer the gates are biased to be off for the un-selected sub-divisions and biased at a second voltage for the selected sub-division, where the second voltage is configured to turn on the lower drain side GIDL select gates and the first voltage is of a higher level than the second voltage.

Select gate bias gradation structure in NAND memory

As block sizes in NAND memory continue to increase in size and density, in can be useful to access less than all of the block, such as sub-block or subset of the blocks NAND strings, in order to reduce read disturbs, reduce power consumption, and increase operating speeds. Although this sort of separation of sub-block can be achieved by independently biasable select gates, the sort of select gate structure can face processing difficulties, particularly at the source side of three dimensional NAND structures. To avoid these difficulties while still providing individually selectable sub-blocks, the following introduces word line based selectors, where multiple word lines of a blocks are programmed with different sets of threshold voltages, allowing them to be biased for individual access of sub-blocks.

Sub-block separation in NAND memory through word line based selectors

A semiconductor structure includes a memory die bonded to a logic die. The memory die includes an alternating stack of insulating layers and electrically conductive layers, a semiconductor material layer located on a distal surface of the alternating stack, a dielectric spacer layer located on a distal surface of the semiconductor material layer, memory opening fill structures vertically extending through the alternating stack, through the semiconductor material layer, and at least partly through the dielectric spacer layer, and a source layer located on a distal surface of the dielectric spacer layer and contacting pillar portions of the vertical semiconductor channels that are embedded within the dielectric spacer layer.

Three-dimensional memory device containing a pillar contact between channel and source and methods of making the same

A vertical layer stack including a bit-line-level dielectric layer and an etch stop dielectric layer can be formed over an array region. Bit-line trenches are formed through the vertical layer stack. Bit-line-trench fill structures are formed in the bit-line trenches. Each of the bit-line-trench fill structures includes a stack of a bit line and a capping dielectric strip. At least one via-level dielectric layer can be formed over the vertical layer stack. A bit-line-contact via cavity can be formed through the at least one via-level dielectric layer and one of the capping dielectric strips. A bit-line-contact via structure formed in the bit-line-contact via cavity includes a stepped bottom surface including a top surface of one of the bit lines, a sidewall segment of the etch stop dielectric layer, and a segment of a top surface of the etch stop dielectric layer.

Three-dimensional memory device containing self-aligned bit line contacts and methods for forming the same

A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over at least one source layer, and groups of memory opening fill structures vertically extending through the alternating stack. Each memory opening fill structure can include a vertical stack of memory elements and a vertical semiconductor channel. A plurality of source-side select gate electrodes can be laterally spaced apart by source-select-level dielectric isolation structures. Alternatively or additionally, the at least one source layer may include a plurality of source layers. A group of memory opening fill structures can be selected by selecting a source layer and/or by selecting a source-level electrically conductive layer.

Three-dimensional memory device with separated source-side lines and method of making the same

A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers, memory opening fill structures including a respective vertical semiconductor channel and a respective vertical stack of memory elements extending through the alternating stack in a memory array region, via contact structures contacting the stepped surfaces of the electrically conductive layers at each step in a staircase region, and a vertical stack of access transistors located between the staircase region and the memory array region.

Lateral transistors for selecting blocks in a three-dimensional memory array and methods for forming the same

A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers, first memory opening fill structures extending through the alternating stack and including a respective first vertical semiconductor channel having a tubular section and a semi-tubular section, second memory opening fill structures, first bit lines electrically connected to a respective subset of the first drain regions, second bit lines electrically connected to a respective subset of the second drain regions, and an erase voltage application circuit configured to electrically bias the first bit lines at a first bit line erase voltage and the second bit lines at a second bit line erase voltage during an erase operation. The first bit line erase voltage is greater than the second bit line erase voltage.

Three dimensional memory device containing truncated channels and method of operating the same with different erase voltages for different bit lines

A method of erasing vertical NAND strings from a source side of the vertical NAND strings includes applying a relatively high erase voltage to a source line, applying a relatively low voltage or 0 V to bit lines, applying a first drain-select-level voltage that is less than the erase voltage to one of the first drain-select-level electrically conductive layers, and applying a second drain-select-level voltage that is greater than the first drain-select-level voltage and not greater than the erase voltage to one of the second drain-select-level electrically conductive layers.

Three-dimensional memory device and method of erasing thereof from a source side

A three-dimensional memory structure includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, an array of memory stack structures extending through the alternating stack, an array of drain select level assemblies overlying the alternating stack and having a same periodicity as the array of memory stack structures, drain select gate electrodes laterally surrounding respective rows of the drain select level assemblies, and a drain select level isolation strip located between a neighboring pair of drain select gate electrodes and including a pair of lengthwise sidewalls. Each of the pair of lengthwise sidewalls includes a laterally alternating sequence of planar sidewall portions andconvexconcavesidewall portions.

On-pitch drain select level isolation structure for three-dimensional memory device and method of making the same

An alternating stack of insulating layers and sacrificial material layers is formed over a substrate. Memory openings are formed through the alternating stack. A layer stack including a charge storage layer, a tunneling dielectric layer, a semiconductor material layer, and a dielectric material layer is formed in the memory openings. The dielectric material layer may include a doped silicate glass layer. A doped silicate glass pillar can be formed at a bottom portion of each memory opening, and a bottom portion of the semiconductor material layer can be converted into a source region by outdiffusion of dopants from the doped silicate glass pillar. Alternatively, the semiconductor material layer can be heavily doped, and can be recessed to form a source region.

Three-dimensional memory devices containing structures for controlling gate-induced drain leakage current and method of making the same

Gate-induced leakage current that is independent of a location of a physical p-n junction between a semiconductor channel and a source/drain region can be provided within a NAND string of a three-dimensional memory device by employing at least one leakage current control circuit that is activated during an erase operation. During the erase operation, an accumulation region and an inversion region can be formed between a vertically-neighboring pair of electrically conductive layers with a depletion region therebetween. The depletion region can generate and inject majority charge carriers into the semiconductor channel during the erase operation. The depletion region can be formed in the source region or in the drain region and may not overlap with a physical p-n junction. Thus, the charge injection location can be independent of the location of the physical p-n junction.

Three-dimensional memory device with depletion region position control and method of erasing same using gate induced leakage

Memory dies configured for multi-stacking within a bonded assembly may be provided without using through-substrate vias that extend through semiconductor substrates. A first memory die may be provided by forming interconnect-side bonding pads on a three-dimensional memory device that overlies a semiconductor substrate. A support die including a peripheral circuitry is boned to the interconnect-side bonding pads. The semiconductor substrate is removed, and array-side bonding pads are formed on an opposite side of the interconnect-side bonding pads. Electrically conductive paths that do not pass through any semiconductor material portion are formed between the interconnect-side bonding pads and the array-side bonding pads, thereby avoiding costly formation of through-substrate via structures that extend through any semiconductor substrate. A second memory die may be bonded to the first memory die to provide stacking of multiple memory dies. Semiconductor substrates may be removed from each memory die upon bonding to a pre-existing assembly.

Semiconductor die stacking using vertical interconnection by through-dielectric via structures and methods for making the same

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Yokkaichi, Japan

Shinsuke Yada