Taiwan Semiconductor Manufacturing Comp. Ltd.

Shinn-Sheng Yu

Anthony Yen

Jeng-Horng Chen

Yen-Cheng Lu

Chih-Tsung Shih

Ru-Gun Liu

Chia-Jen Chen

Chia-Chen Chen

Hsin-Chang Lee

Hsu-Ting Huang

Chung-Ju Lee

Chih-Ming Ke

Chin-Hsiang Lin

Tsai-Sheng Gau

Chia-Hao Hsu

Ming-Feng Shieh

Jeff J Xu

Tsung-Min Huang

Shuo-Yen Chou

Minfeng Chen

Kenji Yamazoe

Jacky Huang

Clement Hsingjen Wann

Shang-Chieh Chien

Shih-Ming Chang

Shao-Ming Yu

Chang-Yun Chang

Pei-Cheng Hsu

Tsung-Yu Chen

Wen-Chuan Wang

Sheng-Chi Chin

Tsiao-Chen Wu

Ping-Chieh Wu

Chieh-Han Wu

Jue-Chin Yu

Tien-Hsi Lee

Burn Jeng Lin

Chun-Kuang Chen

Hung-Chang Hsieh

Chi-Lun Lu

Ting-Hao Hsu

Shu-Hao Chang

Ching-Fang Yu

Chia-Ching Huang

Tao-Min Huang

Hong-Chang Hsieh

Wei-Hung Liu

Hung-Jui Kuo

Tien-I Bao

Ming-Ching Chang

Ta-Cheng Lien

Hua-Tai Lin

Hsin-Chieh Yao

Chih-Cheng Lin

Yao-Ching Ku

Burn-Jeng Lin

Bang-Chein Ho

Jui-Ching Wu

Wei-Chih Lai

Pei-Hung Chen

Chieh-Jen Cheng

Norman Chen

Yu-Fu Lin

Kuo-Chen Huang

Ming-Jiun Yao

Yi-Ling Hsieh

Bang Chein Ho

Chia-Chun Chung

Chia-Tsung Shih

Pei-Chung Hsu

Yu-Hsi Wang

Huan-Tai Lin

Shih-Ying Chen

An extreme ultraviolet lithography (EUVL) method includes providing at least two phase-shifting mask areas having a same pattern. A resist layer is formed over a substrate. An optimum exposure dose of the resist layer is determined, and a latent image is formed on a same area of the resist layer by a multiple exposure process. The multiple exposure process includes a plurality of exposure processes and each of the plurality of exposure processes uses a different phase-shifting mask area from the at least two phase-shifting mask areas having a same pattern.

Photolithography method and apparatus

An extreme ultraviolet lithography method is disclosed. In an example, the EUVL method includes forming a resist layer on a substrate; performing a first exposure process to image a first pattern of a first sub-region of a first mask to the resist layer; performing a second exposure process to image a second pattern of a second sub-region of the first mask to the resist layer; and performing a third exposure process to image a third pattern of a first sub-region of a second mask to the resist layer. The second and third patterns are identical to the first pattern. The first, second and third exposure processes collectively form a latent image of the first pattern on the resist layer.

Lithography method with reduced impacts of mask defects

A method includes generating a diffraction map from a plurality of target patterns, generating a favorable zone and an unfavorable zone from the diffraction map, placing a plurality of sub-resolution patterns in the favorable zone, and performing a plurality of geometric operations on the plurality of sub-resolution patterns to generate modified sub-resolution patterns. The modified sub-resolution patterns extend into the favorable zone, and are away from the unfavorable zone.

Geometric mask rule check with favorable and unfavorable zones

A method of manufacturing a semiconductor device includes dividing a number of dies along an x axis in a die matrix in each exposure field in an exposure field matrix delineated on the semiconductor substrate, wherein the x axis is parallel to one edge of a smallest rectangle enclosing the exposure field matrix. A number of dies is divided along a y axis in the die matrix, wherein the y axis is perpendicular to the x axis. Sequences SNx0, SNx1, SNx, SNxr, SNy0, SNy1, SNy, and SNyr are formed. p*(Nbx+1)−2 stepping operations are performed in a third direction and first sequence exposure/stepping/exposure operations and second sequence exposure/stepping/exposure operations are performed alternately between any two adjacent stepping operations as well as before a first stepping operation and after a last stepping operation. A distance of each stepping operation in order follows the sequence SNx.

Method of manufacturing a semiconductor device and apparatus for manufacturing the semiconductor device

A method of manufacturing a semiconductor device includes dividing a number of dies along an x axis in a die matrix in each exposure field in an exposure field matrix delineated on the semiconductor substrate, wherein the x axis is parallel to one edge of a smallest rectangle enclosing the exposure field matrix. A number of dies is divided along a y axis in the die matrix, wherein the y axis is perpendicular to the x axis. Sequences SNx0, SNx1, SNx, SNxr, SNy0, SNy1, SNy, and SNyr are formed. p*(Nbx+1)&#x2212;2 stepping operations are performed in a third direction and first sequence exposure/stepping/exposure operations and second sequence exposure/stepping/exposure operations are performed alternately between any two adjacent stepping operations as well as before a first stepping operation and after a last stepping operation. A distance of each stepping operation in order follows the sequence SNx.

A method of enhancing a layout pattern includes determining a target layout pattern comprising a disk shape associated with a hole. The method includes defining a polygon having a plurality of vertices on the disk shape. The plurality of vertices coincide with a boundary of the disk shape and the polygon is an initial layout pattern of the hole. The method includes performing an iterative correction of the initial layout pattern. The iterative correction includes projecting the layout pattern of the hole onto a substrate, determining an error between the target layout pattern and the projected layout pattern, and adjusting the layout pattern by moving the vertices of the polygon to generate a next iteration of the layout pattern. The method includes continuing the adjusting, projecting, and determining until a criterion is satisfied and a final iteration of the layout pattern of the hole is generated.

Vertex-based OPC for opening patterning

Photolithography apparatus includes a radiation source, a mask to modify radiation from the radiation source so the radiation exposes photoresist layer disposed on a semiconductor substrate in patternwise manner, a wafer stage, and a controller. The wafer stage supports the semiconductor substrate. The controller determines target total exposure dose for the photoresist layer and target focus position for the photoresist layer; and controls exposure of first portion of the photoresist layer to first exposure dose of radiation at first focus position using first portion of the mask, moving the semiconductor substrate relative to the mask; and exposure of the first portion of the photoresist layer to second exposure dose of radiation using second portion of the mask at second focus position, and exposure of second portion of the photoresist layer to the second exposure dose at the second focus position using the first portion of the mask.

A method of enhancing a layout pattern includes determining a target layout pattern comprising a disk shape pattern associated with an opening. The method includes defining a polygon having a plurality of vertices on the disk shape pattern. The plurality of vertices coincide with a boundary of the disk shape pattern and the polygon is an initial layout pattern of the opening. The method includes performing an iterative correction of the initial layout pattern. The iterative correction includes projecting the layout pattern of the opening onto a substrate, determining an error between the target layout pattern and the projected layout pattern, and adjusting the layout pattern by moving the vertices of the polygon to generate a next iteration of the layout pattern. The method includes continuing the adjusting, projecting, and determining until a criterion is satisfied and a final iteration of the layout pattern of the opening is generated.

Various methods are disclosed herein for reducing (or eliminating) printability of mask defects during lithography processes. An exemplary method includes performing a first lithography exposing process and a second lithography exposing process using a mask to respectively image a first set of polygons oriented substantially along a first direction and a second set of polygons oriented substantially along a second direction on a target. During the first lithography exposing process, a phase distribution of light diffracted from the mask is dynamically modulated to defocus any mask defect oriented at least partially along both the first direction and a third direction that is different than the first direction. During the second lithography exposing process, the phase distribution of light diffracted from the mask is dynamically modulated to defocus any mask defect oriented at least partially along both the second direction and a fourth direction that is different than the third direction.

Method to mitigate defect printability for ID pattern

The present disclosure provides a photolithography mask. The photolithography mask includes a substrate that contains a low thermal expansion material (LTEM). A multilayer (ML) structure is disposed over the substrate. The ML structure is configured to reflect radiation. The ML structure contains a plurality of interleaving film pairs. Each film pair includes a first film and a second film. The first film and the second film have different material compositions. Each film pair has a respective thickness. For at least a subset of the plurality of the film pairs, the respective thicknesses of the film pairs change randomly along a predefined direction.

Mask with multilayer structure and manufacturing method by using the same

A lithography system includes a radiation source configured to generate an extreme ultraviolet (EUV) light. The lithography system includes a mask that defines one or more features of an integrated circuit (IC). The lithography system includes an illuminator configured to direct the EUV light onto the mask. The mask diffracts the EUV light into a 0-th order ray and a plurality of higher order rays. The lithography system includes a wafer stage configured to secure a wafer that is to be patterned according to the one or more features defined by the mask. The lithography system includes a pupil phase modulator positioned in a pupil plane that is located between the mask and the wafer stage. The pupil phase modulator is configured to change a phase of the 0-th order ray.

Extreme ultraviolet lithography system, device, and method for printing low pattern density features

Growing community of inventors

Hsinchu, Taiwan

Shinn-Sheng Yu