Kabushiki Kaisha Toshiba

Shinji Taguchi

Kenji Maeguchi

Kenji Shibata

Homare Matsumura

Kouichi Kanzaki

Youichiro Niitsu

In the CMOS semiconductor device having an epitaxial layer, a trench with an appropriate depth is formed in the vicinity of a boundary between a range in which a MOS transistor is formed and a well range in which another MOS transistor is formed; the inner wall surface of the trench is covered with a thermal oxide film; and the trench is buried with a semiconductor substance, so that two CMOS transistors can be electrically isolated by the trench to increase the latch-up holding voltage beyond a supply voltage (e.g. 5 v). Therefore, the latch-up proof resistance can be increased to protect the device from noise which otherwise would break the device. Further, the trench depth is shallower than the low impurity atom concentration layer (epitaxial layer) or 3 .mu.m but deeper than a value obtained by subtracting 2 .mu.m from the above thickness or 3 .mu.m.

CMOS semiconductor device

A method of manufacturing a semiconductor device is disclosed. In the manufacturing method, an impurity diffusion layer as a first interconnection layer is formed on a semiconductor substrate. Then, an aluminum layer as a second interconnection layer is formed on the semiconductor substrate with an insulating film interposing therebetween. Another insulating layer is further formed on the aluminum layer. An anisotropic etching process is applied to the insulating layer, the second interconnection layer, and the insulating film, thereby forming a contact extending up to the first interconnection layer through these layers, and the insulating film. After the formation of the contact hole, an aluminum layer is formed on the entire surface of the insulating film including the inner surface of the contact hole. The aluminum layer formed in the contact hole electrically interconnects the first and second interconnecting layers.

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Yokohama, Japan

Shinji Taguchi