Sumco Corporation

The University of Tokyo

Nok Corporation

Shinji Okawa

Etsurou Morita

Isoroku Ono

Teruo Fujii

Keiichi Miyajima

Takayuki Komori

SooHyeon Kim

An extracellular potential measurement device includes multiple insulating films each of which is made from an electric insulating material, the insulating films being stacked and bonded to each other; and multiple electrode wires each of which is made from an electroconductive material, the electrode wires being arranged in multiple heights. Each of the electrode wires is interposed between an upper insulating film and a lower insulating film. Each of the insulating films, except for a lowermost insulating film, has an opening penetrating the insulating film. The opening in a lower insulating film has a size that is less than that of the opening in an upper insulating film, the openings in the insulating films being overlapped to form a recess having a size reducing downward, the recess being adapted to store a collection of cells. Each of the electrode wires has an end that is located near an opening in an insulating film that is immediately below the electrode wire, the ends being exposed in the recess.

Extracellular potential measurement device

A direct bonded SOI wafer having an entire buried oxide film layer covered and not exposed is manufactured by: (A) forming a laminated body by laminating a semiconductor wafer and a support wafer via an oxide film; and (B) forming a thin-film single crystal silicon layer on the support wafer using a buried oxide film layer by film-thinning the semiconductor wafer to a predetermined thickness. In a process (C) the entire buried oxide film layer is covered by a main surface on the laminating side of the support wafer and the single crystal silicon layer. The covering of the entire buried film layer is carried out by, between process (A) and (B), removing the oxide film formed on the circumferential end edge of the main surface on the laminating side and the chamfered portion to leave the oxide film only on the laminated surface except the circumferential end edge.

Method for manufacturing direct bonded SOI wafer and direct bonded SOI wafer manufactured by the method

A processing time required for regeneration of a layer transferred wafer is reduced and the regeneration cost is lowered, while a removal amount at the regeneration is decreased the number of regeneration times is increased. A main surface of a semiconductor wafer () has a main flat portion () and a chamfered portion () formed in the periphery of the main flat portion (), an ion implanted area () is formed by implanting ions only into the main flat portion (), a laminated body () is formed by laminating the main flat portion () on a main surface of a support wafer (), and moreover, the semiconductor wafer () is separated from a thin layer () in the ion implanted area () by heat treatment at a predetermined temperature so as to obtain a thick layer transferred wafer (), which is to be regenerated. The main flat portion () of the semiconductor wafer () is formed to have a ring-shape step () protruding from the chamfered portion (), and the semiconductor wafer () is separated from the thin layer () on the whole surface of the ion implanted area () so that no step is generated in the periphery thereby to obtain the layer transferred wafer ().

Process for regeneration of a layer transferred wafer and regenerated layer transferred wafer

Growing community of inventors

Tokyo, Japan

Shinji Okawa