Mitsubishi Denki Kabushiki Kaisha

Mitsubishi Electric Corporation

Shinji Aono

Hideki Takahashi

Tadaharu Minato

Masana Harada

Yoshifumi Tomomatsu

Kazuhiko Nakahara

Kenzo Yamamoto, Legal Representative

Ikuko Yamamoto, Legal Representative

Junichi Moritani

An object of the present invention is to provide a trench gate type IGBT achieving both retention of withstand voltage and lowering of ON-state voltage and to provide a method for manufacturing the trench gate type IGBT. The IGBT according to the present invention is an SJ-RC-IGBT which includes a drift layer having super junction structure, and includes an IGBT area and an FWD area on the rear surface. In the IGBT according to the present invention, a first drift layer has an impurity concentration of 1&#xd7;10atms/cmor higher and lower than 2&#xd7;10atms/cm, and a thickness of 10 &#x3bc;m or larger and smaller than 50 &#x3bc;m; and that a buffer layer has an impurity concentration of 1&#xd7;10atms/cmor higher and lower than 2&#xd7;10atms/cm, and a thickness of 2 &#x3bc;m or larger and smaller than 15 &#x3bc;m.

Insulating gate-type bipolar transistor

A trench gate IGBT designed to reduce on-state voltage while maintaining the withstand voltage, including a first drift layer formed on a first main surface of a buffer layer, a second drift layer of the first conductivity type formed on said first drift layer, a base layer of a second conductivity type formed on the second drift layer, an emitter layer of the first conductivity type selectively formed in the surface of the base layer, and a gate electrode buried from the surface of the emitter layer through into the second drift layer with a gate insulating film therebetween, wherein said first drift layer has a structure in which a first layer of the first conductivity type and a second layer of the second conductivity type are repeated in a horizontal direction.

Insulated gate bipolar transistor and manufacturing method thereof

A carrier storage layer is located in a region of a predetermined depth from a surface of an N&#x2212; substrate, a base region is located in a shallower region than the predetermined depth and an emitter region is located in a surface of the N&#x2212; substrate. The carrier storage layer is formed by phosphorus injected to have a maximum impurity concentration at the predetermined depth, the base region is formed by boron injected to have the maximum impurity concentration at a shallower position than the predetermined depth and the emitter region is formed by arsenic injected to have the maximum impurity concentration at the surface of the N&#x2212; substrate. An opening is formed to extend through the emitter region, base region and the carrier storage layer. On the inner wall of the opening, a gate electrode is formed with a gate insulating film therebetween.

Semiconductor device and manufacturing method thereof

An insulated gate bipolar transistor includes a first main electrode on a first main surface and in contact with a base region of an insulated gate transistor at the first main surface, a first semiconductor layer of a first conductivity type on a second main surface, a second semiconductor layer of a second conductivity type on the second main surface and vertically aligned with a region of the first main electrode in contact with the base region, and a second main electrode formed on the first and second semiconductor layers. An interface between the second main electrode and each of the first and second semiconductor layers is parallel to the first main surface, a distance between the first main surface and the interface is equal to 200 &#x3bc;m or smaller, and a thickness of each of the first and second semiconductor layers is equal to 2 &#x3bc;m or smaller.

Insulated gate bipolar transistor with built-in freewheeling diode

To provide a reverse conducting semiconductor device in which an insulated gate bipolar transistor and a free wheeling diode excellent in recovery characteristic are monolithically formed on a substrate, the free wheeling diode including; a second conductive type base layer to constitute the insulated gate bipolar transistor; a first conductive type base layer for constituting the insulated gate bipolar transistor, an anode electrode which is an emitter electrode covering a first conductive type emitter layer and the second conductive type base layer, a cathode electrode which is a collector electrode covering the first conductive type base layer and a second conductive type collector layer formed on the part of the first conductive type base layer, wherein a short lifetime region is formed on a part of the first conductive type base layer.

Reverse conducting semiconductor device and a fabrication method thereof

It is an object to obtain a semiconductor device comprising a channel stop structure which is excellent in an effect of stabilizing a breakdown voltage and a method of manufacturing the semiconductor device. A silicon oxide film () is formed on an upper surface of an N-type silicon substrate (). An N-type impurity implantation region () is formed in an upper surface () of the N-type silicon substrate () in a portion exposed from the silicon oxide film (). A deeper trench () than the N-type impurity implantation region () is formed in the upper surface () of the N-type silicon substrate (). A silicon oxide film () is formed on an inner wall of the trench (). A polysilicon film () is formed to fill in the trench (). An aluminum electrode () is formed on the upper surface () of the N-type silicon substrate (). The aluminum electrode () is provided in contact with an upper surface of the polysilicon film () and the upper surface () of the N-type silicon substrate (). The aluminum electrode () is extended over the silicon oxide film () to constitute a field plate.

Semiconductor device including a channel stop structure and method of manufacturing the same

A semiconductor device and a manufacturing method therefor are provided, the semiconductor device having a good reverse recovery characteristic, and having no reduction in breakdown voltage because no defect occurs in the upper main surface of a Si substrate even when wires are bonded onto an anode electrode. A semiconductor device includes a Si substrate including an Ncathode layer and an Nlayer. An impurity such as platinum whose barrier height is less than that of silicon is introduced into upper regions of the Nlayer where P anode layers are not formed, thereby forming Schottky junction regions. A barrier metal is formed between the Si substrate and an anode electrode.

An anode electrode metal layer composed of aluminum is formed in a region on the inner side than an anode layer formed on a main surface of a semiconductor substrate. Thus, an impurity diffusion region from the innermost circumferential surface of said surface of field limiting innermost circumferential layer to the outermost circumferential surface of the anode electrode metal layer may be used as an electrical resistance. As a result, the hole density distributed from the bottom side of the field limiting innermost circumferential layer to a cathode layer when forward bias is applied may be reduced. As a result, when a reverse bias is applied, locally great recovery current passed from a cathode layer to the bottom of field limiting innermost circumferential layer may be restrained. Therefore, a diode capable of preventing destruction of a field limiting innermost circumferential layer when a reverse bias is applied may be provided.

Free wheel diode for preventing destruction of a field limiting innermost circumferential layer

This invention provides TEGs for improving accuracy of lifetime evaluation. The TEGs include a base region &lt;Ba&gt; selectively having a cathode region &lt;C&gt; in the surface portion thereof, and an anode region &lt;A&gt;. The intersection of a center line of the cathode region &lt;C&gt; and the anode region &lt;A&gt; provides a function region &lt;WT&gt; located within the range of 5h, five times as much as a height h of a wafer &lt;W&gt;. The function region &lt;WT&gt; makes a pair with the cathode region &lt;C&gt; and actually serves as an actual anode region for the cathode region &lt;C&gt;. As an area ratio of the cathode region &lt;C&gt; to the function region &lt;WT&gt; is smaller, ON voltage values Vf obtained for respective lifetime values get isolated from each other. Thus, the cathode region &lt;C&gt; is formed so that the area ratio of the cathode region &lt;C&gt; to the function region &lt;WT&gt; is about 1/1750000 to 1/4500.

Teg for carrier lifetime evaluation

In a semiconductor device and a method of manufacturing the same, the semiconductor device is provided with an n.sup.+ -type layer located between an n-type buffer layer and a p-type collector layer and having a higher impurity concentration than n-type buffer layer. A diffusion depth of p-type collector layer toward a first main surface is smaller in a first region and is larger in a second region. As a result, the semiconductor device has a sufficiently reduced turn-off loss.

Semiconductor device and method of manufacturing the same

A loaded line phase shifter includes a semiconductor substrate; a main transmission line one-quarter wavelength long disposed on the semiconductor substrate; loaded lines connected to opposite ends of the main line; first and second FETs with drain electrodes connected to the other ends of the loaded lines and grounded source electrodes; and a resonant circuit including a third FET and an inductor connected between the drain electrodes of said first and second FETs. A desired phase shift quantity of the phase shifter is determined by the characteristic impedance of the main line, the reactance components of the loaded lines, and the off-capacitances of the FETs. When the resonant circuit is closed in this structure, the susceptance of the loaded lines and the first and second FETs is equal to zero, resulting in a phase shift quantity equivalent to half of the phase shift quantity obtained when the resonant circuit is opened. Therefore, two different phase shift quantities are achieved in one phase shifter, resulting in a small-sized multiple-bit phase shifter.

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Tokyo, Japan

Shinji Aono