Adv Antest Corporation

Shinichiro Kuroe

Minoru Kobayashi

A delay time stabilization circuit is used in a timing generator which provides a reference timing of a semiconductor IC test system. The delay time stabilization circuit includes a delay control circuit, a period generator which generates period signals necessary for DUT (device under test) testing, a loop forming switch, and a period counter 31 for counting the period in a loop circuit. The calibration process starts by setting the loop forming switch. A start pulse generation circuit generates n pulses when receiving one trigger pulse which pass through a CMOS variable delay circuit and the loop circuit to a 1/n divider circuit. The n pulses are divided by n to produce a signal pulse which triggers the start pulse generation circuit. In the DUT testing, the period generator 11 generates the period signal necessary for the testing which is the same repetition rate as generated by the start pulse generation circuit, resulting in the same power dissipation in the calibration process and the DUT testing.

Delay time stabilization circuit

A timing calibration circuit includes a plurality of variable delay circuits each of which is assigned to one of test signal paths to regulate a phase delay time for a signal passing therethrough, a multiplexer for selecting one of the test signal paths whose inputs are connected to outputs of drivers, a signal path whose one end is connected to all of test contactors and the other end is connected to the multiplexer, a counter for measuring phase delay times in a first feedback loop which does not include the signal path and a second feedback loop which includes the signal path with respect to each of the test signal paths. The counter measures a phase delay time for the first feedback loop to determine a reference value so that a phase delay time in the first feedback loop for other test signal paths is adjusted by the variable delay circuit to be equal to the reference value, and the counter measures a phase delay time for the second feedback loop to determine a calibration value for each of the test signal paths and record the calibration value.

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Gyoda, Japan

Shinichiro Kuroe