Mitsubishi Electric Corporation

Shingo Sudo

Tatsuo Ota

Nobutake Taniguchi

Hironori Kashimoto

Hiroshi Yoshida

Taketoshi Shikano

Yuichiro Suzuki

Takamasa Iwai

Minoru Egusa

Erubi Suzuki

Kazuyuki Hashimoto

An ultrasonic bonding apparatus includes an ultrasonic bonding machine having an ultrasonic tool for applying an ultrasonic wave to a bonding target member mounted on a fixed object fixed to a jig, while pressing a bonding member against the bonding target member; and a bonding inspection apparatus for inspecting a bonding quality of the bonding target member and the bonding member. The bonding inspection apparatus includes: a bonded-state measuring device for detecting a vibration in the jig or a housing of the ultrasonic bonding machine equipped with the jig, to thereby output a detection signal; and a bonded-state determination device for determining, in a bonding process for the bonding target member and the bonding member, a bonded state between the bonding target member and the bonding member on the basis of the detection signal outputted by the bonded-state measuring device.

Ultrasonic bonding apparatus, ultrasonic bonding inspection method and ultrasonically-bonded portion fabrication method

In a power semiconductor device, power semiconductor elements are mounted on a large die pad and the like. The large die pad is joined to a power lead via a lead stepped portion. The large die pad has a first end portion and a second end portion located with a distance therebetween in the X axis direction. In the Y axis direction, the lead stepped portion is joined to the first end portion side relative to a central line between the first end portion and the second end portion. The large die pad is inclined such that a distance between the large die pad and the first main surface of the molding resin is longer from the first end portion toward the second end portion.

Power semiconductor device, method for manufacturing power semiconductor device, and power conversion device

A semiconductor device has a substrate, a semiconductor element, an electrode lead, and a sealing resin portion. The substrate has a main surface on which a circuit pattern is formed. The semiconductor element has first and second surfaces, and is arranged on the substrate such that the first surface faces the main surface. The electrode lead has one end joined to the circuit pattern and the other end joined by soldering to the second surface. The other end has a plurality of portions divided from each other. The sealing resin portion seals the semiconductor element and the electrode lead. Thus, there can be provided a semiconductor device that has relieved thermal stress at a joining portion of the electrode lead, and therefore is less subject to fatigue failure.

Semiconductor device

A semiconductor device which includes a radiating plate, a wiring patterned layer on the radiating plate via an insulating layer, at least one semiconductor chip mounted on the wiring patterned layer. The semiconductor chip has a surface electrode. The semiconductor device further includes a conductive lead plate electrically connected with the surface electrode of the semiconductor chip, and a resin package of thermoplastic resin having anisotropic linear expansion coefficient varying based upon directions. The resin package covers the wiring patterned layer, the semiconductor chip, the conductive lead plate, and at least a portion of the radiating plate. The conductive lead plate extends in a direction which provides the resin package with the maximum linear expansion coefficient. In the semiconductor device so structured, the warpage of the resin package is reduced both in longitudinal and transverse directions.

Semiconductor device with thermoplastic resin to reduce warpage

One of the aspects of the present invention is to provide a semiconductor device, which includes a base plate, an insulating substrate on the base plate, and a wiring patterned layer on the insulating substrate. Also, it includes at least one semiconductor chip bonded on the wiring patterned layer, the semiconductor chip having a surface electrode. A main terminal is connected via a conductive adhesive layer onto at least either one of the surface electrode and the wiring patterned layer. Also, a resin package covers the insulating substrate, the wiring patterned layer, the semiconductor chip, the conductive adhesive layer, and at least a portion of the main terminal.

Growing community of inventors

Tokyo, Japan

Shingo Sudo