Toshiba Memory Corporation

Kabushiki Kaisha Toshiba

Kioxia Corporation

Shingo Nakajima

Hiroyasu Tanaka

Masayuki Akou

Hidenobu Nagashima

Ryota Asada

Mitsuhiro Noguchi

Eiji Ito

Hanae Ishihara

Akitsugu Hatazaki

Ming Hu

Takashi Izumi

Toshiyuki Takewaki

A semiconductor device according to one embodiment includes: a semiconductor substrate; a peripheral circuit provided on the semiconductor substrate; and a stacked body provided above the peripheral circuit, which has a memory cell array. The peripheral circuit includes: a metal film including silicon; a silicide film stacked on the metal film; and a barrier metal film stacked on the silicide film.

Semiconductor device and manufacturing method thereof

According to one embodiment, a semiconductor device includes a substrate, an interconnect layer, a layer stack, and a first silicon nitride layer. The interconnect layer includes a transistor provided on the substrate and a first interconnect electrically coupled to the transistor and is provided above the transistor. The layer stack is provided above the interconnect layer and includes conductive layers stacked with an insulation layer interposed between two of conductive layers of each pair of conductive layers. The first silicon nitride layer is provided between the interconnect layer and the layer stack.

Semiconductor device and method of manufacturing the same

The memory device includes a conductive layer, a plurality of first electrode layers stacked over the conductive layer and spaced from each other in a first direction, a semiconductor layer extending through the first electrode layers in the first direction, a second electrode layer provided between the conductive layer and the first electrode layers, and a semiconductor base, located between the conductive layer and the semiconductor layer and extending through the second electrode layer, wherein the semiconductor base has a first width at a portion thereof extending through the second electrode layer in the first direction and second width at a portion thereof connected to the semiconductor layer, and the first width is greater than the second width.

Memory device and manufacturing methods thereof

An integrated circuit device includes an insulating film, a contact extending in a first direction and being provided inside the insulating film, and an insulating member. A composition of the insulating member is different from a composition of the insulating film. A level difference is formed in a side surface of the contact, a portion of a region of the side surface other than the level difference contacts the insulating film. The insulating member contacts the level difference.

Integrated circuit device and method for manufacturing same

According to the embodiments, the semiconductor memory device includes a semiconductor substrate, a first conducting layer, a semiconductor layer, a plurality of second conducting layer, and an electric charge accumulating layer. The first conducting layer is disposed on the semiconductor substrate via an insulating layer. The semiconductor layer is disposed on the first conducting layer and extends in a first direction above the semiconductor substrate. The plurality of the second conducting layers extends in a second direction intersecting with the first direction, and is laminated along the first direction via an insulating layer, and is disposed on the first conducting layer. The electric charge accumulating layer is disposed between the semiconductor layer and the plurality of second conducting layer. The semiconductor substrate includes an n type semiconductor region facing an end portion of the semiconductor layer.

Semiconductor memory device

According to one embodiment, a semiconductor memory device includes a stacked body; a semiconductor body; a charge storage layer; a first conductor; a second conductor; and a third conductor. The stacked body includes a plurality of electrode layers stacked with an insulator interposed. The semiconductor body extends along a stacking direction of the stacked body. The first conductor is provided in the stacked body. The first conductor is in contact with the substrate. The second conductor includes a different material from the first conductor. The second conductor is in contact with a first portion of the first conductor. The third conductor includes a same material as the second conductor. The third conductor is in contact with a second portion of the first conductor.

When a first wiring and/or a second wiring is formed, a connection portion is formed in the first wiring and/or the second wiring which covers a part of a lower electrode layer outside the memory cell array. An etching suppressing portion is formed above the connection portion. A contact hole is formed in which a portion under the etching suppressing portion reaches up to a connection potion, and the other portion reaches up to the lower electrode layer by performing etching to a laminated body in a range including the etching suppressing portion. The laminated body includes the insulating layer, the first wiring, a memory cell layer, the second wiring, and the etching suppressing portion. The contact layer is formed by burying a conductive material in the contact hole.

Semiconductor memory device, method of manufacturing the same and method of forming contact structure

A semiconductor memory device having a first wiring layer which is provided on a first insulator, and which extends in a first direction, and a non-volatile memory cell which is provided in a pillar shape on the first wiring layer, and which includes a non-ohmic element and variable resistance element connected in series. The resistance value of the variable resistance element changes in accordance with a voltage or current applied thereto. A barrier layer is provided on the memory cell and is configured in an in-plane direction. A conductive layer is provided on the barrier layer and is configured in an in-plane direction. A second insulator is provided on the first insulator and covers side surfaces of the memory cell, the barrier layer, and the conductive layer. A second wiring layer is provided on the conductive layer and extends in a second direction.

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Yokkaichi, Japan

Shingo Nakajima