Taiwan Semiconductor Manufacturing Comp. Ltd.

Shing-Long Lee

Julie Huang

Chia Shiung Tsai

Cheng-Hao Huang

So Wein Kuo

Yeong-Rong Chang

Cuker Huang

May-Ho Ko

Weng Liang Fang

Chia-Ling Lee

Yi-Jou Lu

The disclosure generally relates to a method for method for plasma etching a substrate in a plasma reactor comprising positioning the substrate on an electrostatic chuck inside the plasma reactor; supplying a DC voltage to the chuck, the DC voltage forming an electrostatic charge buildup on the substrate; plasma etching the substrate; disconnecting the DC voltage to the chuck; and counteracting the electrostatic charge buildup on the substrate by discharging a varying RF signal within the chamber.

Method and apparatus for dynamic plasma treatment of bipolar ESC system

Within a method for forming a microelectronic fabrication, there is first provided a substrate. There is then formed over the substrate a blanket aluminum containing conductor layer. There is then formed over the blanket aluminum containing conductor layer a masking layer. There is then etched, while employing a plasma etch method, the blanket aluminum containing conductor layer to form a patterned aluminum containing conductor layer while employing the masking layer as an etch mask layer, where the plasma etch method employs an etchant gas composition comprising at least one fluorine containing etchant gas and at least one halogen containing etchant gas other than a fluorine containing etchant gas. There is then formed contacting the patterned aluminum containing conductor layer a conformal dielectric liner layer. There is then formed upon the conformal dielectric liner layer a spin-on-glass (SOG) planarizing layer. Finally, there is then thermally annealed the spin-on-glass (SOG) planarizing layer to form a thermally cured spin-on-glass (SOG) planarizing layer. By employing the at least one fluorine containing etchant gas in conjunction with the at least one halogen containing etchant gas other than the fluorine containing etchant gas within the etchant gas composition for forming from the blanket aluminum containing conductor layer the patterned aluminum containing conductor layer, there is attenuated a delamination of the thermally cured spin-on-glass (SOG) planarizing layer from the conformal dielectric liner layer.

Method for forming a delamination resistant multi-layer dielectric layer for passivating a conductor layer

The present invention discloses a method for forming DRAM stacked capacitors by utilizing a densified oxide layer as an etch-stop for the wet etching process of an upper oxide layer in forming a contact hole for the stacked capacitor and thus, eliminating the need of a silicon nitride etch-stop layer and the occurrence of numerous processing difficulties normally observed in such stacked capacitor forming process. The lower oxide layer can be formed by a BPTEOS chemistry while the upper oxide layer can be formed by an ozone-TEOS chemistry.

Method for forming DRAM stacked capacitor

A method is described which uses the differential etch behaviour of two different kinds of sequentially deposited silicon oxide layers in conjunction with controlled thicknesses and etching conditions to allow the etching of features such as via contact holes, oxide sidewalls, and crossover insulation edges to produce non-abrupt step height profiles for better edge coverage while still maintaining close adherence to minimum spacing design ground rules between adjacent features.

Method for edge profile and design rules control

A method for forming a patterned fluorine containing plasma etched layer within a microelectronics fabrication. There is first provided a substrate employed within a microelectronics fabrication. There is then formed over the substrate a fluorine containing plasma etchable layer. There is then formed upon the fluorine containing plasma etchable layer a patterned photoresist layer. There is then etched through a fluorine containing plasma etching method while employing the patterned photoresist layer as a photoresist etch mask layer the fluorine containing plasma etchable layer to form a patterned fluorine containing plasma etched layer. The patterned fluorine containing plasma etched layer has a fluoropolymer residue layer formed thereupon. The fluorine containing plasma etch method employs a first etchant gas composition comprising a nitrogen trifluoride etchant gas. Finally, there is stripped through an oxygen containing plasma stripping method the patterned photoresist layer and the fluoropolymer residue layer from the patterned fluorine containing plasma etched layer. The oxygen containing plasma stripping method employs a second etchant gas composition comprising a fluorine containing etchant gas and an oxygen containing etchant gas.

Plasma etch method for forming residue free fluorine containing plasma

A method for avoiding oxide peeling by removing polymer contaminants from the edge of a wafer is described. An interlevel dielectric sandwich layer is formed by depositing a first oxide layer overlying semiconductor device structures in and on a semiconductor substrate, coating a spin-on-glass layer overlying the first oxide layer and rinsing the spin-on-glass layer whereby an edge bead rinse hump is formed a first distance from the edge of the wafer, etching back the spin-on-glass layer wherein the wafer is held by a clamp a second distance from the edge of the wafer wherein the second distance is smaller than the first distance and wherein the etching back of the spin-on-glass layer forms the polymer on the surface of the first oxide layer under the clamp at a third distance between the first and second distances, and depositing a second oxide layer overlying the etched back spin-on-glass layer and the polymer at the edge of the wafer to complete the interlevel dielectric sandwich layer. A layer of photoresist is coated overlying the sandwich layer wherein the photoresist layer does not extend closer to the edge of the wafer than the third distance and patterned to form a photoresist mask. The interlevel dielectric sandwich layer is etched away where it is not covered by the mask to form via openings wherein the second oxide layer overlying the polymer is etched away. The photoresist mask is stripped whereby the polymer is also removed thereby avoiding oxide peeling at the edge of the wafer.

Growing community of inventors

Hsin-Chu, Taiwan

Shing-Long Lee