Taiwan Semiconductor Manufacturing Comp. Ltd.

Shing-Chyang Pan

Ching-Hua Hsieh

Szu-Ping Tung

Tze-Liang Lee

Jung-Hau Shiu

Jen Hung Wang

Chung-Chi Ko

Cheng-Lin Huang

Jing-Cheng Lin

Keng-Chu Lin

Hsien-Ming Lee

Ching-Yu Chang

Yuan-Chih Hsieh

Hai-Dang Trinh

Li-Lin Su

Yi-Ren Wang

Wan-Lin Tsai

Shau-Lin Shue

Shwang-Ming Jeng

Szu-Hua Wu

Jung-Tang Wu

Meng-Yu Wu

Wei-Ren Wang

Chun-Wen Cheng

Cheng-Yuan Tsai

Ming-Hsing Tsai

Kuei-Sung Chang

Chih-Hao Chen

Fei-Lung Lai

Chao-Hsien Peng

Yu-Kai Lin

Chia Cheng Chou

Chun-Kai Chen

Albert Zhong

Chen-Hua Douglas Yu

Wen-Chih Chiou

Syun-Ming Jang Jang

Mong-Song Liang

Chii-Ming M Wu

Yu-Yun Peng

Chih-Chien Chi

Yao-Jen Chang

Victor Y Lu

Chih-Tsung Lee

Wen-Cheng Yang

Ya-Ling Lee

Kuan-Chia Chen

Hong-Hui Hsu

Shao-Lin Shue

Shih-Chang Chen

Chih-Wei Chang

Hung-Wen Su

Wei-Jung Lin

Huang-Yi Huang

Ting-Chu Ko

Sung-En Lin

Chia-Cheng Chou

Shih-Wei Chou

Han-Hsin Kuo

Hsueh-Hung Fu

Tsung-Hsun Huang

Jen-Hung Wang

Yu-Chun Huang

Grace H Ho

Shwangming Jen

Chin-Piao Chang

Shwangming Jing

Kuo-Wei Cheng

A sputtering system includes a vacuum chamber, a power source having a pole coupled to a backing plate for holding a sputtering target within the vacuum chamber, a pedestal for holding a substrate within the vacuum chamber, and a time of flight camera positioned to scan a surface of a target held to the backing plate. The time of flight camera may be used to obtain information relating to the topography of the target while the target is at sub-atmospheric pressure. The target information may be used to manage operation of the sputtering system. Managing operation of the sputtering system may include setting an adjustable parameter of a deposition process or deciding when to replace a sputtering target. Machine learning may be used to apply the time of flight camera data in managing the sputtering system operation.

Physical vapor deposition chamber with target surface morphology monitor

A semiconductor device includes a substrate, a first conductive feature over a portion of the substrate, and an etch stop layer over the substrate and the first conductive feature. The etch stop layer includes a silicon-containing dielectric (SCD) layer and a metal-containing dielectric (MCD) layer over the SCD layer. The semiconductor device further includes a dielectric layer over the etch stop layer, and a second conductive feature in the dielectric layer. The second conductive feature penetrates the etch stop layer and electrically connects to the first conductive feature.

Etch stop layer for semiconductor devices

Some embodiments relate to a method for forming an integrated chip. The method includes forming a bottom electrode over a substrate. A data storage layer is formed on the bottom electrode. A diffusion barrier layer is formed over the data storage layer. The diffusion barrier layer has a first diffusion activation temperature. A top electrode is formed over the diffusion barrier layer. The top electrode has a second diffusion activation temperature less than the first diffusion activation temperature.

Diffusion barrier layer in programmable metallization cell

Various embodiments of the present disclosure are directed towards a microelectromechanical system (MEMS) device. The MEMS device includes a dielectric structure disposed over a first semiconductor substrate, where the dielectric structure at least partially defines a cavity. A second semiconductor substrate is disposed over the dielectric structure. The second semiconductor substrate includes a movable mass, where opposite sidewalls of the movable mass are disposed between opposite sidewall of the cavity. An anti-stiction structure is disposed between the movable mass and the dielectric structure, where the anti-stiction structure is a first silicon-based semiconductor.

Microelectromechanical systems device having a mechanically robust anti-stiction/outgassing structure

Semiconductor devices and methods of forming semiconductor devices are provided. A method includes forming a first mask layer over an underlying layer, patterning the first mask layer to form a first opening, forming a non-conformal film over the first mask layer, wherein a first thickness of the non-conformal film formed on the top surface of the first mask layer is greater than a second thickness of the non-conformal film formed on a sidewall surface of the first mask layer, performing a descum process, wherein the descum process removes a portion of the non-conformal film within the first opening, and etching the underlying layer using the patterned first mask layer and remaining portions of the non-conformal film as an etching mask.

Patterning methods for semiconductor devices

A structure includes a substrate, a transistor, a contact, an oxygen-free etch stop layer, an oxygen-containing etch stop layer, a dielectric layer, and a via. The transistor is on the substrate. The contact is on a source/drain region of the transistor. The oxygen-free etch stop layer spans the contact. The oxygen-containing etch stop layer extends along a top surface of the oxygen-free etch stop layer. The dielectric layer is over the oxygen-containing etch stop layer. The via passes through the dielectric layer, the oxygen-containing etch stop layer, and the oxygen-free etch stop layer and lands on the contact. The memory stack lands on the via.

Memory device and method for fabricating the same

A semiconductor structure includes a conductive feature, a first metal-based etch-stop layer over the underlying structure, a metal-free etch-stop layer over the first metal-based etch-stop layer, a second metal-based etch-stop layer over the metal-free etch-stop layer, an interlayer dielectric layer over the second metal-based etch-stop layer, and an interconnect structure extending through the first metal-based etch-stop layer, metal-free etch-stop layer, and the second metal-based etch-stop layer, wherein a bottom portion of the conductive interconnect structure directly contacts the conductive feature. The first metal-based etch-stop layer may include a first metallic component having one of aluminum, tantalum, titanium, or hafnium, and the second metal-based etch-stop layer may include a second metallic component the same as or different from the first metallic component. The first metal-based etch-stop layer and the second metal-based etch-stop layer may both be free of silicon.

Metal-based etch-stop layer

Various embodiments of the present disclosure are directed towards a method for manufacturing an integrated chip, the method comprises forming an interconnect structure over a semiconductor substrate. An upper dielectric layer is formed over the interconnect structure. An outgas layer is formed within the upper dielectric layer. The outgas layer comprises a first material that is amorphous. A microelectromechanical systems (MEMS) substrate is formed over the interconnect structure. The MEMS substrate comprises a moveable structure directly over the outgas layer.

Structure for microelectromechanical systems (MEMS) devices to control pressure at high temperature

Some embodiments relate to a memory device. The memory device includes a bottom electrode overlying a substrate. A data storage layer overlies the bottom electrode. A top electrode overlies the data storage layer. A conductive bridge is selectively formable within the data storage layer to couple the bottom electrode to the top electrode. A diffusion barrier layer is disposed between the data storage layer and the top electrode.

A memory device includes a semiconductor substrate, a first dielectric layer, a metal contact, an aluminum nitride layer, an aluminum oxide layer, a second dielectric layer, a metal via, and a memory stack. The first dielectric layer is over the semiconductor substrate. The metal contact passes through the first dielectric layer. The aluminum nitride layer extends along a top surface of the first dielectric layer and a top surface of the metal contact. The aluminum oxide layer extends along a top surface of the aluminum nitride layer. The second dielectric layer is over the aluminum oxide layer. The metal via passes through the second dielectric layer, the aluminum oxide layer, and the aluminum nitride layer and lands on the metal contact. The memory stack lands on the metal via.

Growing community of inventors

Hsinchu County, Taiwan

Shing-Chyang Pan