Taiwan Semiconductor Manufacturing Comp. Ltd.

Shin-Yi Yang

Ming-Han Lee

Shau-Lin Shue

Yu-Chen Chan

Shu-Wei Li

Hsiang-Huan Lee

Meng-Pei Lu

Ching-Fu Yeh

Tz-Jun Kuo

Chin-Lung Chung

Guanyu Luo

Hsin-Ping Chen

Hsi-Wen Tien

Hai-Ching Chen

Tai-I Yang

Ming Han Lee

Han-Tang Hung

Chia-Tien Wu

Hsin-Yen Huang

Yung-Hsu Wu

Min Cao

Chih-Wei Lu

Yung-Chih Wang

Hsien-Chang Wu

Pei-Yin Liou

Chia-Hao Chang

Chung-Ju Lee

Cheng-Chi Chuang

Pinyen Lin

Sung-Li Wang

Cheng-Hsiung Tsai

Shuen-Shin Liang

Chia-Hung Chu

Wei-Chen Chu

Chao-Hsien Peng

Po-Chin Chang

Hung-Yi Huang

Chun-Hung Liao

Li-Lin Su

Chieh-Han Wu

Hwei-Jay Chu

Tzu-Hui Wei

Yuting Cheng

Tzu Pei Chen

An-Dih Yu

Harry Chien

Cian-Yu Chen

Yun-Chi Chiang

Andy Li

Provided are devices with conductive contacts and methods for forming such devices. A method includes forming a lower conductive contact in a dielectric material and over a structure, wherein the lower conductive contact has opposite sidewalls that extend to and terminate at a top surface. The method also includes separating an upper portion of each sidewall from the dielectric material and locating a barrier material between the upper portion of each sidewall and the dielectric material. Further, the method includes forming an upper conductive contact over the lower conductive contact.

Conductive structure interconnects with downward projections

A semiconductor device includes a semiconductor substrate, a plurality of intercalated graphene structures and a via. The intercalated graphene structures are disposed over the semiconductor substrate. Each of the intercalated graphene structures includes a plurality of graphene layers each extending substantially parallel to the semiconductor substrate. The via extends into at least a portion of one of the intercalated graphene structures toward the semiconductor substrate, and is in contact with edges of corresponding ones of the graphene layers of the one of the intercalated graphene structures.

Semiconductor device including graphene interconnect and method of making the semiconductor device

A semiconductor device includes a substrate and an interconnect layer disposed over the substrate. The interconnect layer includes an interconnect structure which includes a topological material. The topological material includes a topological insulator, a topological semimetal, or a combination thereof. A method for manufacturing the semiconductor device is also disclosed.

Interconnect structure including topological material

Embodiments of the present disclosure provide an integrated circuit die having edge interconnect features. The edge interconnect features may be conductive lines extending through sealing rings and into scribe line regions. In some embodiments, heterogeneous integrated circuit dies with edge interconnect features are fabricated on the same substrate. Edge interconnect features of the neighboring integrated circuit dies are connected to each other and provide direct connections between the integrated circuit dies without going through an interposer.

Semiconductor packages and methods for forming the same

The present disclosure relates to an integrated chip. The integrated chip includes a substrate. A first conductive feature is over the substrate. A second conductive feature is over the substrate and is adjacent to the first conductive feature. The first and second conductive features are separated by a cavity. A dielectric liner extends from the first conductive feature to the second conductive feature along a bottom of the cavity and further extends along opposing sidewalls of the first and second conductive features. A dielectric cap covers and seals the cavity. The dielectric cap has a top surface that is approximately planar with top surfaces of the first and second conductive features. The first conductive feature and the second conductive feature comprise graphene intercalated with one or more metals.

Integrated chip with graphene based interconnect

A semiconductor device includes a first underlying metal line and a second underlying metal line in a first dielectric layer over a substrate. The semiconductor device includes a first metal feature and a second metal feature in a second dielectric layer over the first dielectric layer. The first metal feature is over and connected to the first underlying metal line, and the second metal feature is over and connected to the second underlying metal line. The first metal feature has a first dimension, the second metal feature has a second dimension, the second dimension being greater than the first dimension. The first metal feature includes a first metal having a first mean free path, the second metal feature includes a second metal having a second mean free path, and the second mean free path is greater than the first mean free path.

Interconnect structures having varied materials

A method includes forming a trench within a dielectric layer, the trench comprising an interconnect portion and a via portion, the via portion exposing an underlying conductive feature. The method further includes depositing a seed layer within the trench, depositing a carbon layer on the seed layer, performing a carbon dissolution process to cause a graphene layer to form between the seed layer and the underlying conductive feature, and filling a remainder of the trench with a conductive material.

Graphene barrier layer for reduced contact resistance

A method for forming a semiconductor structure includes following operations. A hybrid layered structure is formed. The hybrid layered structure includes at least a 2D material layer and a first 3D material layer. Portions of the hybrid layered structure are removed to form a plurality of conductive features and at least an opening between the conductive features. A dielectric material is formed to fill the opening and to form an air gap sealed within.

Method for forming semiconductor structure

Embodiments of the present disclosure provide a stacking edge interconnect chiplet. In one embodiment, a semiconductor device is provided. The semiconductor device includes a first integrated circuit die comprising a first device layer having a first side and a second side opposite the first side, a first interconnect structure disposed on the first side of the first device layer, and a second interconnect structure disposed on the second side of the first device layer. The semiconductor device also includes a power line extending through the first device layer and in contact with the first interconnect structure and the second interconnect structure, and a second integrated circuit die disposed over the first integrated circuit die, the second integrated circuit die comprising a third interconnect structure in contact with the second interconnect structure of the first integrated circuit die.

An interconnect structure is provided. The interconnect structure includes a first metal line. The first metal line includes a first conductive material disposed within a first dielectric layer over a substrate and a second conductive material disposed within the first dielectric layer and directly over a top of the first conductive material. The second conductive material is different from the first conductive material. A second dielectric layer is disposed over the first dielectric layer. A first via comprising a third conductive material is disposed within the second dielectric layer and on a top of the second conductive material. The second conductive material and the third conductive material have lower diffusion coefficients than the first conductive material.

Hybrid interconnect structure for self aligned via

An interconnect structure and methods of forming the same are described. In some embodiments, the structure includes a first dielectric layer and one or more first conductive features disposed in the first dielectric layer. The one or more first conductive features includes a first metal. The structure further includes a plurality of graphene layers disposed on each of the one or more first conductive features, the plurality of graphene layers include a second metal intercalated therebetween, and the second metal is different from the first metal.

Interconnect structure and methods of forming the same

Embodiments of the present disclosure provide an integrated circuit die with vertical interconnect features to enable direct connection between vertically stacked integrated circuit dies. The vertical interconnect features may be formed in a sealing ring, which allows higher routing density than interposers or redistribution layer. The direct connection between vertically stacked integrated circuit dies reduces interposer layers, redistribution process, and bumping processes in multi-die integration, thus, reducing cost of manufacturing.

Embodiments of the present disclosure provide a semiconductor package. In one embodiment, the semiconductor package includes a first integrated circuit die having a first circuit design, and the first integrated circuit die comprises a first device layer and a first interconnect structure. The semiconductor package also includes a second integrated circuit die having a second circuit design different than the first circuit design, and the second integrated circuit die comprises a second device layer and a second interconnect structure having a first side in contact with the first device layer and a second side in direct contact with the first interconnect structure of the first integrated circuit die. The semiconductor package further includes a substrate having a first side bonded to the first interconnect structure, wherein the second integrated circuit die is surrounded by at least a portion of the substrate.

Embodiments of the present disclosure provide a method for forming a semiconductor package. In one embodiment, the method includes providing a first integrated circuit die having a first circuit design on a substrate, providing a second integrated circuit die having a second circuit design on the substrate, wherein the first and second integrated circuit dies are separated from each other by a scribe line. The method also includes forming a first interconnect structure on a first surface of the first integrated circuit die, forming a second interconnect structure on a first surface of the second integrated circuit die, extending a power rail from a second surface of the first integrated circuit die to a first side of a source/drain (S/D) feature, forming one or more power lines through an entire thickness of the first and second integrated circuit dies, respectively, forming a third interconnect structure on the second surface of the first integrated circuit die, and forming a fourth interconnect structure on the second surface of the second integrated circuit die.

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Taipei, Taiwan

Shin-Yi Yang