Macronix International Co., Ltd.

Shin-Yi Tsai

Ming-Chung Liang

Henry Wei-Ming Chung

Chun-Hung Lee

Henry Chung

Chien-Wei Chen

Chia-Chi Chung

Hsu-Sheng Yu

Jiun-Ren Lai

An-Chi Wei

Kuo-Liang Wei

Jen-Jiann Chiou

A semiconductor manufacturing method that includes depositing a first layer over a substrate, providing a layer of hardmask over the first layer, patterning and defining the hardmask layer to form at least two hardmask structures, wherein each hardmask structure includes at least one substantially vertical sidewall and one substantially horizontal top, and wherein the hardmask structures are separated by a first space, depositing a photo-insensitive material over the at least two hardmask structures and the first layer, wherein an amount of the photo-insensitive material deposited on the top of the hardmask structures is substantially greater than an amount of the photo-insensitive material deposited on the at least one sidewall of the hardmask structures, wherein the hardmask structures with the photo-insensitive layer on the sidewalls thereof are separated by a second space, and wherein the first space is greater than the second space.

Method for reducing dimensions between patterns on a hardmask

A semiconductor manufacturing method that includes providing a substrate, providing a layer of material over the substrate, providing a layer of photoresist over the material layer, patterning and defining the photoresist layer, depositing a layer of polymer over the patterned and defined photoresist layer, wherein the layer of polymer is conformal and photo-insensitive, and etching the layer of polymer and the layer of material.

Method for reducing dimensions between patterns on a photoresist

A method of reducing pattern pitch is provided. A material layer, a hard mask layer and a patterned photoresist layer are sequentially formed over a substrate. Using the patterned photoresist layer as etching mask, the hard mask layer is etched. Due to the trenching effect, a residual hard mask layer remains in an exposed region exposed by the photoresist layer and micro-trenches are formed at the edges of the residual hard mask layer. Thereafter, using the residual hard mask layer as etching mask to pattern the material layer. Finally, the patterned photoresist layer and the hard mask layer are removed. In the invention, the trenching effect is utilized when etching the hard mask layer. A portion of the hard mask layer remains, and the micro-trenches are formed in the hard mask layer. After the micro-trenches are transferred to the material layer, the pattern pitch can be reduced.

Method of reducing pattern pitch in integrated circuits

A semiconductor manufacturing method that includes defining a substrate, depositing a polysilicon layer over the substrate, depositing a layer of photoresist over the polysilicon layer, patterning and defining the photoresist layer, depositing a layer of inorganic material over the patterned and defined photoresist layer, wherein the layer of inorganic material is conformal and photo-insensitive, and anisotropic etching the layer of inorganic material and the layer of semiconductor material.

The present invention generally relates to a dual damascene processing method using a silicon rich oxide (SRO) layer thereof and its structure. In the dual damascene process, a first dielectric layer, an etching stop layer, such as a silicon rich oxide layer, and a second dielectric layer are sequentially formed on a semiconductor substrate, which is provided with metal connections therein. Then, the present invention utilizes photolithography and etching technique to obtain a dual damascene structure profile having a trench and a via hole. The present invention uses the silicon rich oxide layer as the etching stop layer so as the present invention can achieve a better trench microloading and better bottom profile. Beside, the present invention does not increase the dielectric constant index (K) of the inter metal dielectric (IMD).

Dual damascene processing method using silicon rich oxide layer thereof and its structure

An operating method of a semiconductor etcher includes three steps. The first step is to provide a first power for shortening a warm-up time of the etcher. The second step is to provide a second power, which is lower than the first power, to perform an etching process. The third step is to provide a third power, which is between the first and second power, for cleaning the etcher.

Operating method of a semiconductor etcher

An apparatus for cleaning a semiconductor wafer is disclosed to substantially improve the efficiency of the cleaning process, and reduce the quantity of cleaning solvent used. The apparatus includes a rotating table for supporting the wafer, a rotation device to rotate the rotation table, a movable or stationary curved-slab for scrubbing the surface of the wafer efficiently, a cleaning nozzle for applying a cleaning solvent or stripper on the surface of the wafer, and a resistance wall for preventing the cleaning solvent spun out from the wafer to pollute the cleaning room.

Apparatus for cleaning a wafer with shearing stress from slab with curved portion

The present invention generally relates to provide a fabrication method for forming a rounded corner of a contact window or a via by using a two-step light etching technique. In the present invention, after the etching process to form the contact window or the via, an object of the invention is to utilize oxygen plasma and fluorocarbon plasma of the two-step light etching technique to produce the rounded corner of the window or via so as this rounded opening profile of the contact window or the via can supply for following metal-filling processes.

Fabrication method for forming rounded corner of contact window and via by two-step light etching technique

A method of etching a metallic layer having an anti-reflection layer thereon. The method includes performing a first etching operation using a fixed set of processing parameters to etch the anti-reflection layer and remove a specified thickness of the metallic layer. Thereafter, a second etching operation is conducted to etch the remaining metallic layer.

Method of etching semiconductor metallic layer

A method of fabricating an insulating layer starts by forming at least one gate, having at least a conductive layer and a cap oxide layer, on a surface of a semiconductor substrate. An insulating layer thicker than a height of the gate on the semiconductor substrate is then formed to follow the topography of the gate to produce an uneven surface. A planar layer is then formed on the insulating layer to form an approximately flat surface for the semiconductor substrate. By performing a planarization process, a portion of the planar layer is removed down to the surface of the insulating layer. A first etching process is then performed to completely remove the remaining portions of the planar layer. Finally, a second etching process is performed to remove the insulating layer and the cap oxide layer atop the gate, so that the remaining insulating layer outside the gate has a protrusive surface after the second etching process.

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Hsinchu, Taiwan

Shin-Yi Tsai