Taiwan Semiconductor Manufacturing Comp. Ltd.

Shin-Rung Lu

Yen-Di Tsen

Jong-I Mou

Chen-Yen Huang

Chih-Wei Hsu

Yi-Ping Hsieh

Ai-Jen Hung

Yung-Yao Lee

Chun-Hsien Lin

Jo Fei Wang

Yu-Jen Cheng

Andy Tsen

Yi-Chuan Lo

Ying Ying Wang

Jin-Ning Sung

Wen-Pin Liu

Wen-Yao Hsieh

Shui-Tien Lin

Ho-Ku Lan

Tsai-Fu Ou

Chih Ming Hong

Shun-Ping Wang

Kun-Hong Lin

In some embodiments, the present application is directed to a method and system for process control of a lithography tool. The method transfers a reference pattern to exposure fields of a reference workpiece to form pairs of overlapping reference layers. Misalignment between the overlapping reference layers is measured to form first and second baseline maps, and a &#x394; baseline map is formed from the first and second baseline maps. A production pattern is transferred to exposure fields of a production workpiece to form second production layers arranged over and aligned to first production layers. Misalignment between the first and second production layers is measured to form a production map. The &#x394; baseline map is transformed and subsequently added to the production map, to form a final production map. Parameters of a process tool are updated based on the final production map.

Intra-field process control for lithography

Some embodiments of the present disclosure relate to a method of alignment which includes defining a plurality of fields on the face of a wafer, and organizing the plurality of fields into an orthogonal field structure and two or more continuous field structures. A first number of alignment structure positions are measured within each field of the two or more continuous field structures, and a second number of alignment structure positions are measured within each field of the orthogonal field structure, the second number being greater than the first number. The feature or layer is then aligned to the previously formed feature or layer based upon the measured alignment structure positions of the two or more continuous field structures and the orthogonal field structure.

Lithographic overlay sampling

A calibration apparatus is provided. The calibration apparatus includes a wafer carrier configured to support a substrate with a patterned layer. The patterned layer includes a first exposure area and remaining exposure areas, and each of the first and the remaining exposure areas includes a first checking mark. The calibration apparatus also includes a measurement device configured to obtain a first exposure value of the first checking mark of the first exposure area by measuring the first checking mark of the first exposure area. The calibration apparatus also includes a processing module configured to calculate first calculated values of the first checking marks of the remaining exposure areas according to the first exposure value and a standard file. The illumination device is adjusted by an adjustment device of the lithography apparatus according to the first calculated values during a lithography process.

Calibration apparatus and an adjustment method for a lithography apparatus

A method of semiconductor fabrication is provided. The method includes providing a model for a device parameter of a wafer as a function of first and second process parameters. The first and second process parameters correspond to different wafer characteristics, respectively. The method includes deriving target values of the first and second process parameters based on a specified target value of the device parameter. The method includes performing a first fabrication process in response to the target value of the first process parameter. The method includes measuring an actual value of the first process parameter thereafter. The method includes updating the model using the actual value of the first process parameter. The method includes deriving a revised target value of the second process parameter using the updated model. The method includes performing a second fabrication process in response to the revised target value of the second process parameter.

Dynamic compensation in advanced process control

A method of processing first and second semiconductor wafers is provided. Each of the first and second semiconductor wafers has a first layer and a second layer over the first layer. A first lithographic process is performed on the first layer over the first semiconductor wafer using a first inter-field correction and a first intra-field correction. An overlay error of the first lithographic process is determined. A second inter-field correction and a second intra-field correction are computed based on the first inter-field correction, the first intra-field correction, and the measured overlay error. A second lithographic process is performed on the second layer over the second semiconductor wafer, based on the second inter-field correction and the second intra-field correction.

Scanner overlay correction system and method

A method includes performing a semiconductor fabrication process on a plurality of substrates. The plurality of substrates are divided into a first subset and a second subset. A rework process is performed on the second subset of the plurality of substrates but not on the first subset. A respective mean value of at least one exposure parameter for a lithography process is computed for each respective one of the first and second subsets of the plurality of substrates. A scanner overlay correction and a mean correction are applied to expose a second plurality of substrates on which the rework process has been performed. The mean correction is based on the computed mean values.

A method for improving alignment in a photolithography machine is provided. The method comprises identifying first empirical alignment data that has been determined from use of a target photomask within at least one non-target tool, and identifying second empirical alignment data that has been determined from use of a non-target photomask within a target tool. The method continues by identifying third empirical alignment data that has been determined from use of a non-target photomask within at least one non-target tool, and calculating from the first, second, and third empirical alignment data a predicted alignment data for the target photomask with the target tool. The method then proceeds by aligning the target photomask within the target tool using the predicted alignment data, exposing a pattern from the target photomask onto the wafer in the target tool, and further processing the exposed wafer.

Method and system for improved overlay correction

A method includes performing a lithography process on a wafer to form a patterned photo resist, and measuring the wafer to determine an overlay error of the patterned photo resist. A high/low specification is determined using the overlay error. An overlay process value setting is generated and compared with the high/low specification to determine whether the overlay process value setting is within a range defined by the high/low specification.

Defense system in advanced process control

The present disclosure provides a semiconductor manufacturing method. The method includes providing product data of a product, the product data including a sensitive product parameter; searching existing products according to the sensitive product parameter to identify a relevant product from the existing products; determining an initial value of a processing model parameter to the product using corresponding data of the relevant product; assigning the initial value of the processing model parameter to a processing model associated with a manufacturing process; thereafter, tuning a processing recipe using the processing model; and performing the manufacturing process to a semiconductor wafer using the processing recipe.

Advanced process control for new tapeout product

A method for photolithography in semiconductor device manufacturing comprises defining test critical dimension target for a photolithography mask, measuring a mask critical dimension, comparing mask critical dimension to the test critical dimension target and determining a critical dimension deviation, determining a photolithography light base energy in response to the critical dimension deviation, and exposing the wafer according to the photolithography light base energy.

System and method for photolithography in semiconductor manufacturing

A method for patterning passivation layers including providing a semiconductor wafer comprising metal interconnects; forming a dielectric passivation layer on the metal interconnects; forming a photosensitive polymeric passivation layer on the dielectric passivation layer; patterning the photosensitive polymeric passivation layer in a first patterning process to form a first opening revealing a portion of the dielectric passivation layer; and, patterning the portion of the dielectric passivation layer in a second patterning process to form at least a second opening in the dielectric passivation layer.

Method for patterning and etching a passivation layer

A method is provided for forming features in a polyimide layer that is employed as an insulating layer or buffer layer during the fabrication of semiconductor devices or chip packaging structures. A pattern is formed in a photosensitive layer that has a high film retention after the development step and a crosslinked network that strengthens and stabilizes it for subsequent processing. The process involves exposing a negative tone photosensitive layer with a first exposure dose that is less than the normal dose used to image the material. The exposed layer is developed to provide a scum free substrate. A second exposure dose then strengthens the formed image by crosslinking unreacted components. First and second exposure doses are determined from a plot of film thickness loss vs. exposure energy. The method applies to photosensitive polyimide precursors as well as negative photoresists that are crosslinked by free radical or chemical amplification mechanisms.

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Chu-Pei, Taiwan

Shin-Rung Lu