Fudan University

Shijin Ding

Wei Zhang

Pengfei Wang

Qingqing Sun

Wenjun Liu

Sun Yang Chen

Yongping Wang

Xingmei Cui

Shibing Qian

Anan Zuo

Kejia Qian

A multi-level cell thin-film transistor memory and a method of fabricating the same, a structure of which memory comprises sequentially from down to top: a gate electrode, a charge blocking layer, a charge trapping layer, a charge tunneling layer, an active region, and source and drain electrodes; wherein the charge tunneling layer fully encloses the charge trapping layer so as to completely isolate the charge trapping layer from the ambience, which prevents change of physical properties and chemical compositions of the charge trapping layer during the annealing treatment, reduces loss of charges stored in the charge trapping layer, and enhances data retention property and device performance stability; a metal oxide semiconductor thin film is utilized as the charge trapping layer of the memory, which implements multi-level cell storage and improves storage density.

Multi-level cell thin-film transistor memory and method of fabricating the same

A method and corresponding reactor for depositing metal-nitride thin film with adjustable metal contents. The method includes several first and second half reaction process. By adjusting the ratio of first and second half reaction cycles, metal nitride thin films with different metal contents can be grown. The first half reaction process is the decomposition of metal-organic precursor adsorbed on the substrate surface, leaving behind metal atom layer by light irradiation. The second half reaction process forms metal nitride thin films by the reaction of NHplasma and the metal atomic layer on the substrate surface. This method can control the ratio between metal and nitrogen atom content in the film, thus achieving the regulation of film resistivity. In addition, this method offers favorable film step coverage and accurate film thickness control capability, which is significantly applicable for the film meeting the requirement of advanced CMOS integrated circuit technology.

Method and corresponding reactor for preparing metal nitrides with adjustable metal contents

A semiconductor memory device with a buried drain is provided. The device comprises a semiconductor substrate (); one drain region () of a first doping type; two source regions () of a second doping type; and a stacked gate provided on the semiconductor substrate for capturing electrons. A memory array formed by a plurality of semiconductor memory devices and a manufacturing method thereof are also provided. The semiconductor memory device has the advantages of small cell area, simple manufacturing process and the like. The manufacturing cost of the memory device is reduced and the storing density of the memory device is increased.

Semiconductor memory device with a buried drain and its memory array

The invention relates to a thin film transistor memory and its fabricating method. This memory using the substrate as the gate electrode from bottom to up includes a charge blocking layer, a charge storage layer, a charge tunneling layer, an active region of the device and source/drain electrodes. The charge blocking layer is the ALD grown AlOfilm. The charge storage layer is the two layer metal nanocrystals which include the first layer metal nanocrystals, the insulating layer and the second layer metal nanocrystals grown by ALD method in sequence from bottom to up. The charge tunneling layer is the symmetrical stack layer which includes the SiO/HfO/SiOor AlO/HfO/AlOfilm grown by ALD method in sequence from bottom to up. The active region of the device is the IGZO film grown by the RF sputtering method, and it is formed by the standard lithography and wet etch method. The TFT memory in this invention has the advantage with large P/E window, good data retention, high P/E speed, stable threshold voltage and simple fabricating process.

Thin film transistor memory and its fabricating method

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Shanghai, China

Shijin Ding