United Microelectronics Corp.

Other

Shih-Wei Sun

Water Lur

Tri-Rung Yew

Chih-Chien Liu

Juan-Yuan Wu

Ta-Shan Tseng

Tony Lin

Wen-Bin Shieh

Jih-Wen Chou

Yimin Huang

J Y Wu

Ellis Lee

Jiunh-Yuan Wu

Shih-Fang Tzou

Jiunn-Hsiung Liao

Ming-Sheng Yang

Wen-Yi Hsieh

Wen-Kuan Yeh

Pei-Yu Chou

Meng-Jin Tsai

Kun-Chih Wang

Jacob Chen

Meng-Chang Liu

Tsang-Jung Lin

H J Wu

Kuen-Jian Chen

Tsao-Ching Tsai

Wen Bin Shieh

Chung-Shien Kao, Deceased

W B Shieh

Yu-Hao Chen

Disclosed is a power regulating apparatus, which is connected between an AC power and a load, for supplying the regulated AC power to the load. The power regulating apparatus includes a first regulating means provided to regulate the input AC power source when the AC power is at a normal power level, and a second regulating means provided to transmit an electric power to the load from a power storage means when the AC power is at a power level lower than the normal power level. Thus, the power regulating apparatus is capable of providing the load with an expected high quality electric power in all cases of AC power variation.

Power regulating apparatus

A method for depositing dielectric material into gaps between wiring lines in the formation of a semiconductor device includes the formation of a cap layer and the formation of gaps into which high density plasma chemical vapor deposition (HDPCVD) dielectric material is deposited. First and second antireflective coatings may be formed on the wiring line layer, the first and second antireflective coatings being made from different materials. Both antireflective coatings and the wiring line layer are etched through to form wiring lines separated by gaps. The gaps between wiring lines may be filled using high density plasma chemical vapor deposition.

High density plasma chemical vapor deposition process

A CMOS device is provided, comprising a substrate, a first-type MOS transistor, a second-type MOS transistor, a first stress layer, a first liner layer, and a second stress layer. The substrate has a first active area and a second active area, which are separated by an isolation structure. Further, the first-type MOS transistor is disposed on the first active area of the substrate, and the second-type MOS transistor is disposed on the second active area of the substrate. The first stress layer is compliantly disposed on the first-type MOS transistor of the first active area. The first liner layer is compliantly disposed on the first stress layer. The second stress layer is compliantly disposed on the second-type MOS transistor of the second active area.

CMOS device and fabricating method thereof

An improved dual damascene structure is provided for use in the wiring-line structures of multi-level interconnects in integrated circuit. In this dual damascene structure, low-K (low dielectric constant) dielectric materials are used to form both the di-electric layers and the etch-stop layers between the metal interconnects in the IC device. With this feature, the dual damascene structure can prevent high parasite capacitance to occur therein that would otherwise cause large RC delay to the signals being transmitted through the metal interconnects and thus degrade the performance of the IC device. With the dual damascene structure, such parasite capacitance can be reduced, thus assuring the performance of the IC device.

Dual damascene structure for the wiring-line structures of multi-level interconnects in integrated circuit

An interconnect structure has a substrate having devices already formed thereon. A dielectric layer covers over the substrate. A conductive structure having at least two substructure separated by an air gap is formed on the dielectric layer. A capping layer covers the conductive structure and the air gap. The capping layer at a portion above the air gap also fills into the air gap by a predetermined distance. The air gap may also extend into the dielectric layer to have a greater height. An etching stop layer is formed on the capping layer. An inter-metal dielectric layer is formed on the etching stop layer. The inter-metal dielectric layer, the etching stop layer and the capping layer are patterned to form an opening that exposes a top surface of the conductive structure. The opening may also expose a top portion of a sidewall of the conductive structure if a misalignment occurs, but the opening does not expose the air gap due to protection from the predetermined distance of the capping layer within the air gap. A next level of conductive structure can be formed to fill the opening. A liner layer can be also formed on a sidewall of the substructure interfacing the air gap, so as to protect the conductive structure.

Interconnect structure with air gap compatible with unlanded vias

Method for forming an interconnect structure with air gap compatible with unlanded vias

A method for chemical mechanical polishing a component includes providing an oxide layer and forming at least one via through the oxide layer. A tungsten layer is formed within the via and over the oxide layer. A first chemical mechanical polishing step is carried out on a polishing pad using a first slurry having an oxidizing component and having a pH of approximately 2 to approximately 4 to remove the tungsten layer from over the oxide layer. A second chemical mechanical polishing step is carried out on the polishing pad using a second slurry having a pH of approximately 2 to approximately 4 to polish scratches out of the oxide layer.

Chemical mechanical polishing methods using low pH slurry mixtures

A multilevel interconnect structure is formed which uses air as a dielectric between wiring lines and which is compatible with the presence of unlanded vias in the interconnect structure. A layer of carbon is deposited over an insulating surface and then a pattern for trenches is formed in the surface of the layer of carbon. Metal is deposited in the trenches and over the layer of carbon and then a chemical mechanical polishing process is used to define wiring lines. An ashing or etch back process is performed on the carbon layer to recess its surface below the surfaces of the wiring lines. An oxide capping layer is provided over the recessed surface of the carbon and the wiring lines, for example using HSQ and curing, and then the carbon layer is consumed through the capping layer using an oxidation process. Air replaces the sacrificial carbon layer during the consumption reaction. Next, a silicon nitride etch stop layer is provided over the surface of the capping layer and then an intermetal dielectric layer is provided. A via is formed by etching through the intermetal dielectric, stopping on the etch stop layer, and then etching through the etch stop layer and the capping layer in distinct processes. The via is filled with a metal plug and then second level wiring lines are formed.

Interconnect structure with gas dielectric compatible with unlanded vias

An improved dual damascene structure is provided for use in the wiring-line structures of multi-level interconnects in integrated circuit. In this dual damascene structure, low-K (low dielectric constant) dielectric materials are used to form both the dielectric layers and the etch-stop layers between the metal interconnects in the IC device. With this feature, the dual damascene structure can prevent high parasite capacitance to occur therein that would otherwise cause large RC delay to the signals being transmitted through the metal interconnects and thus degrade the performance of the IC device. With the dual damascene structure, such parasite capacitance can be reduced, thus assuring the performance of the IC device.

A method of forming bonding pad commences by forming a conformal barrier layer on a provided inter-metal dielectric layer. A first metal layer is formed on the barrier layer to partially fill the trench. A thin glue layer is formed on the first metal layer. A second metal layer is formed on the glue layer to fill the trench. The second metal layer, the glue layer, the first metal layer and the barrier layer are partially removed to expose the dielectric layer. A bonding pad structure is thus formed in the trench. The bonding pad structure comprises a first metal pad and a second metal pad.

Method of forming bonding pad

An integrated circuit including a dielectric layer over a substrate and a via formed through the dielectric layer exposing a conductive region in the substrate. A first conductive layer is formed over the dielectric layer and within the via. Etching through a portion of the first conductive layer is carried out to form first and second individual conducting regions separated from one another by a first exposed portion of the dielectric layer having a first width. A second conductive layer is formed over the first and second individual conducting regions, over the first exposed portion of the dielectric layer, and filling any unfilled via regions. Etching the second conducting layer is carried out to expose a portion of the dielectric layer for a second time and to V form first and second wiring lines. The first wiring line includes the first conducting region and first remaining portions of the second conductive layer, and the second wiring line including the second conducting region and second remaining portions of the second conducting layer. The presence of the remaining portions of the second conductive layer as part of the wiring lines effectively decreases the size of the gap between the wiring lines and promotes subsequent gap-filling.

Metallization for uncovered contacts and vias

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Taipei, Taiwan

Shih-Wei Sun