Taiwan Semiconductor Manufacturing Comp. Ltd.

Shih Wei Bih

Yen-Yu Chen

Chun-Chih Lin

Chih-Wei Lin

Wen-Hao Cheng

Sheng-Wei Yeh

Chung-Liang Cheng

Han-Wen Liao

Xuan-You Yan

Yi-Ming Dai

Chia-Hsi Wang

Yi-Chih Chen

A polysilicon layer is formed over a substrate. The polysilicon layer is etched to form a dummy gate electrode having a top portion with a first lateral dimension and a bottom portion with a second lateral dimension. The first lateral dimension is greater than, or equal to, the second lateral dimension. The dummy gate electrode is replaced with a metal gate electrode.

Reducing metal gate overhang by forming a top-wide bottom-narrow dummy gate electrode

A semiconductor device includes: a first conductive structure having sidewalls and a bottom surface, the first conductive structure extending through one or more isolation layers formed on a substrate; and an insulation layer disposed between at least one of the sidewalls of the first conductive structure and respective sidewalls of the one or more isolation layers, wherein the first conductive structure is electrically coupled to a second conductive structure through at least the bottom surface.

Interconnect structure and method for forming the same

The present disclosure provides an integrated circuit (IC) structure. The IC structure includes a semiconductor substrate; an interconnection structure formed on the semiconductor substrate; and a redistribution layer (RDL) metallic feature formed on the interconnection structure. The RDL metallic feature further includes a barrier layer disposed on the interconnection structure; a diffusion layer disposed on the barrier layer, wherein the diffusion layer includes metal and oxygen; and a metallic layer disposed on the diffusion layer.

Redistribution layer metallic structure and method

A physical vapor deposition (PVD) target for performing a PVD process is provided. The PVD target includes a backing plate and a target plate coupled to the backing plate. The target plate includes a sputtering source material and a dopant, with the proviso that the dopant is not impurities in the sputtering source material. The sputtering source material includes a diffusion barrier material.

PVD target design and semiconductor devices formed using the same

Interconnect structure and method of forming the same

A gate structure includes a gate dielectric layer over a semiconductor workpiece. The gate structure further includes a work function layer over the gate dielectric layer, wherein the work function layer has a U-shape profile. The gate structure further includes an adhesion layer over the work function layer, wherein a surface of the adhesion layer farthest from the work function layer is substantially free of oxygen atoms. The gate structure further includes a conductive layer over the adhesion layer, wherein the conductive layer has an I-shape profile.

Semiconductor device with adhesion layer

A method of making a semiconductor device includes forming an opening in a dielectric layer. The method further includes depositing a barrier layer in the opening. The method further includes depositing an adhesion layer over the barrier layer. The method further includes treating the adhesion layer using a hydrogen-containing plasma.

Semiconductor device with adhesion layer and method of making

The present disclosure provides an apparatus for fabricating a semiconductor device with target sputtering, including a chamber for accommodating a consumable target, a target accumulative consumption counter, wherein the target accumulative consumption counter provides a signal correlated to an amount of the consumable target being consumed, and a power supply communicates with the consumable target counter, wherein the power supply provides a power output according to the signal.

Apparatus for fabricating a semiconductor device with target sputtering and target sputtering method for fabricating the semiconductor device

Interconnect structure with insulation layer and method of forming the same

A method of fabricating a semiconductor structure includes depositing a dielectric layer over a gate stack, removing a portion of the gate stack to form a trench in the dielectric layer, depositing an insulating layer in the trench, depositing an adhesion layer over the insulating layer, and performing a hydrogen-containing plasma treatment on the adhesion layer.

Method of fabricating semiconductor device with adhesion layer

The present disclosure describes an bonding pad formation method that incorporates an tantalum (Ta) conductive layer to block mobile ionic charges generated during the aluminum-copper (AlCu) metal fill deposition. For example, the method includes forming one or more interconnect layers over a substrate and forming a dielectric over a top interconnect layer of the one or more interconnect layers. A first recess is formed in the dielectric to expose a line or a via from the top interconnect layer. A conductive layer is formed in the first recess to form a second recess that is smaller than the first recess. A barrier metal layer is formed in the second recess to form a third recess that is smaller than the second recess. A metal is formed to fill the third recess.

Growing community of inventors

Taichung, Taiwan

Shih Wei Bih