Taiwan Semiconductor Manufacturing Comp. Ltd.

Other

National Science Council

Shih-Tzung Chang

Ying-Lang Wang

Kei-Wei Chen

Yu-Ku Lin

Ting-Chun Wang

Shih-Ho Lin

Hsi-Kuei Cheng

Kuo-Hsiu Wei

Hung-Ju Chien

Hsien-Ping Feng

Chin-Hao Su

Chu-Chang Chen

Hsun-Chang Chan

Chi-Wen Liu

Jung-Chih Tsao

Chun-Chang Chen

Lin-June Wu

Po-Jen Shih

Tao Cheng

Ming-Shih Tsai

Chao-Lung Chen

Tong-Hua Kuan

Bau-Tong Dai

Jiun-Pyng You

Ming-Wen Chen

Ching-Hwan Su

Chung-Chang Chen

Jchung-Chang Chen

Yu-Kin Lin

Wen-Hsin Huang

Ming-Jei Lee

An integrated circuit having post passivation interconnections with a second connection pattern is disclosed. A passivation layer (preferably made of a non-oxide material) is formed over the integrated circuit already having a first plurality of contact pads in a first connection pattern. A buffer layer is then formed over the passivation layer. The buffer layer preferably is a silicon oxide layer with a thickness substantially smaller than a thickness of the passivation layer. A post passivation metal layer is deposited over the buffer layer. A second plurality of contact pads as part of the second connection pattern is formed in the post passivation metal layer.

Semiconductor devices having post passivation interconnections and a buffer layer

A novel test device and method for calibrating the alignment of a laser beam emitted from a laser metrology tool with respect to a target area on a substrate. The test device includes a laser-sensitive material having a calibration pattern that includes a target point. When the tool is properly adjusted, the laser beam strikes the target point and is released to production. If the laser beam misses the target point, the tool is re-adjusted and re-tested until the laser beam strikes the target point.

Test device and method for laser alignment calibration

An electropolishing method for removing potential device-contaminating particles from a wafer, is disclosed. The method includes immersing the wafer in an electropolishing electrolyte solution and removing defects and particles from the wafer by rotational friction between the wafer and the electrolyte solution in combination with electrolysis. The method is effective in removing particles from via openings of all sizes, including via openings having a width smaller than about 0.2 &#x3bc;m.

Electropolishing method for removing particles from wafer surface

A method for forming a copper dual damascene with improved copper migration resistance and improved electrical resistivity including providing a semiconductor wafer including upper and lower dielectric insulating layers separated by a middle etch stop layer; forming a dual damascene opening extending through a thickness of the upper and lower dielectric insulating layers wherein an upper trench line portion extends through the upper dielectric insulating layer thickness and partially through the middle etch stop layer; blanket depositing a barrier layer including at least one of a refractory metal and refractory metal nitride to line the dual damascene opening; carrying out a remote plasma etch treatment of the dual damascene opening to remove a bottom portion of the barrier layer to reveal an underlying conductive area; and, filling the dual damascene opening with copper to provide a substantially planar surface.

Method of forming barrier layer with reduced resistivity and improved reliability in copper damascene process

A method of forming post passivation interconnects for an integrated circuit is disclosed. A passivation layer of a non-oxide material is formed over the integrated circuit. A buffer layer is then formed over the passivation layer. The buffer layer preferably is a silicon oxide layer with a thickness substantially smaller than a thickness of the passivation layer. A post passivation metal layer is deposited over the buffer layer and a connection pattern is formed in the post passivation metal layer.

Method for reducing defects in post passivation interconnect process

For 0.18 micron technology, it is common practice to use silicon oxynitride as an anti-reflective layer for defining the via etch patterns. It has however been found that, using current technology, residual particles of oxynitride get left behind. The present invention solves this problem by subjecting the surface from which the silicon oxynitride was removed to a high pressure rinse of an aqueous solution that includes a surfactant such as tetramethyl ammonium hydroxide or isopropyl alcohol. These surfactants serve to modify the hydrophobic behavior of the silicon oxynitride particles so that they no longer cling to the surface.

Removal of SiON residue after CMP

A method and system is disclosed for reducing slurry usage in a chemical mechanical polishing operation utilizing at least one polishing pad thereof. Slurry can be intermittently supplied to a chemical mechanical polishing device. The slurry is generally flushed so that a portion of said slurry is trapped in a plurality of pores of at least one polishing pad associated with said chemical mechanical polishing device, wherein only a minimum amount of said slurry necessary is utilized to perform said chemical mechanical polishing operation, thereby reducing slurry usage and maintaining a consistent level of slurry removal rate performance and a decrease in particle defects thereof. The present invention thus discloses a method and system for intermittently delivering slurry to a chemical mechanical polishing device in a manner that significantly conserves slurry usage.

Method and system for slurry usage reduction in chemical mechanical polishing

A method for improving thickness uniformity on a semiconductor wafer during a chemical mechanical polishing process capable of eliminating a wafer edge collapsing defect is described. In the method, slurry solution is removed from a peripheral edge portion of less than 10 mm wide on the surface of the polishing pad such that a concentration of the slurry can be effectively reduced in the peripheral region. The reduced slurry solution leads to a reduction in the removal rate on the wafer surface. The removal of slurry from the peripheral region can further be achieved by a mechanical means. A suitable width of the peripheral region of the polishing pad to be sprayed by an edge sprayer is less than 10 mm, and preferably between about 3 mm and about 5 mm. A suitable solvent to be sprayed is deionized water.

Method for improving thickness uniformity on a semiconductor wafer during chemical mechanical polishing

A process for preparing a surface of a lower level metal structure, exposed at the bottom of a sub-micron diameter opening, to allow a low resistance interface to be obtained when overlaid with an upper level metal structure, has been developed. A disposable, capping insulator layer is first deposited on the composite insulator layer in which the sub-micron diameter opening will be defined in, to protect underlying components of the composite insulator from a subsequent metal pre-metal procedure. After anisotropically defining the sub-micron diameter opening in the capping insulator, and composite insulator layers, and after removal of the defining photoresist shape, an argon sputtering procedure is used to remove native oxide from the surface of the lower level metal structure. In addition to native oxide removal the argon sputtering procedure, featuring a negative DC bias applied to the substrate, also removes the capping insulator layer from the top surface of the composite insulator layer. An in situ metal deposition then allows a clean interface to result between the overlying metal layer, and the underlying plasma treated, metal surface.

Use of a capping layer to reduce particle evolution during sputter pre-clean procedures

Slurry formulationf or CMP of organic-added low SOG dielectric was development. The SOG layers with various amount of organic content are subject to polish experiments using silica- and zirconia-based slurries with a variety of additives. The results indicate that, as the amount of organic content in SOG increases, CMP polish rate drops with silica-based KOH-added slurry. On the other hand, zirconia-based slurry could result in higher plish rate for both SOG (>400 nm/min) and thermal oxide. Polish selectivity ranging from 1.2 to 9.1 can be achieved by adding various amount of tetra-alkyl in ammonium hydroxide.

Slurry formulation for selective CMP of organic spin-on-glass insulating layer with low dielectric constant

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Taichung, Taiwan

Shih-Tzung Chang