Taiwan Semiconductor Manufacturing Comp. Ltd.

Shih-Ting Hung

Shin-Puu Jeng

Po-Yao Chuang

Yi-Wen Wu

Po-Hao Tsai

Techi Wong

Meng-Liang Lin

Ching-Feng Fu

Hsien-Wen Liu

Chen-Hua Douglas Yu

Chen-Yi Lee

Chen-Nan Yeh

Cheng-Hung Chang

Clement Hsingjen Wann

Harry-Hak-Lay Chuang

Chih-Hsin Ko

Bao-Ru Young

Wei Cheng Wu

Hsin-Chih Chen

Chia Ming Liang

Meng-Fang Hsu

Kong-Pin Chang

Chih-Hsien Lin

Yu-Rung Hsu

Hsiang-Tai Lu

Dai-Jang Chen

Chih-Hao Wang

Po-Yao Lin

Ming-Chih Yew

Wei-Hao Wu

Yao-Chun Chuang

Chia-Kuei Hsu

Kai-Chieh Yang

Chia-Wei Su

Yi-Hsuan Hsiao

Yi-Jou Lin

Po-Chin Chang

Yinlung Lu

Jyun-Lin Wu

Tzu-Jui Fang

Inez Fu

Gloria Wu

Shih-Yung Peng

A package structure includes a redistribution structure, a first semiconductor die, a first passive component, a second semiconductor die, a first insulating encapsulant, a second insulating encapsulant, a second passive component and a global shielding structure. The redistribution structure includes dielectric layers and conductive layers alternately stacked. The first semiconductor die, the first passive component and the second semiconductor die are disposed on a first surface of the redistribution structure. The first insulating encapsulant is encapsulating the first semiconductor die and the first passive component. The second insulating encapsulant is encapsulating the second semiconductor die, wherein the second insulating encapsulant is separated from the first insulating encapsulant. The second passive component is disposed on a second surface of the redistribution structure. The global shielding structure is surrounding the first insulating encapsulant, the second insulating encapsulant, and covering sidewalls of the redistribution structure.

Package structure

Methods for improving joinder between a surface-mount package and a printed circuit board are disclosed. The warpage at a corner of the surface-mount package and at a corresponding corner of a joint area on the printed circuit board are measured to determine the degree of mismatch. A mini-pad is applied to the corner between the surface-mount package and the joint area on the printed circuit board. The thickness of the mini-pad pushes against the surface-mount package and the printed circuit board, reducing the degree of mismatch below a critical dimension of a ball grid array of the surface-mount package. The surface-mount package can then be soldered to the joint area, reducing or preventing the formation of solder bridges and short circuits.

Methods and systems for improving surface mount joinder

A semiconductor package is provided. The semiconductor package includes a redistribution structure, a semiconductor die, and an interposer structure. The interposer structure includes an insulating base having a first surface facing the semiconductor die and a second surface opposite to the first surface and conductive features formed over the insulating base. The conductive features include first portions on the first surface of the insulating base and vertically overlapping the semiconductor die, second portions on the first surface of the insulating base and located outside a projection area of the semiconductor die in a top view, third portions on the second surface of the insulating base and vertically overlapping the semiconductor die, and fourth portions on the second surface of the insulating base and located outside the projection area of the semiconductor die in the top view. The interposer structure includes capping layers and dielectric features.

Semiconductor package with improved interposer structure

A semiconductor package is provided. The semiconductor package includes an encapsulating layer, a semiconductor die formed in the encapsulating layer, and an interposer structure covering the encapsulating layer. The interposer structure includes an insulating base having a first surface facing the encapsulating layer, and a second surface opposite the first surface. The interposer structure also includes insulating features formed on the first surface of the insulating base and extending into the encapsulating layer. The insulating features is arranged in a matrix and faces a top surface of the semiconductor die. The interposer structure further includes first conductive features formed on the first surface of the insulating base and extending into the encapsulating layer. The first conductive features surround the matrix of the insulating features.

An integrated fan-out package includes a first redistribution structure, a die, a plurality of conductive structures, an encapsulant, and a second redistribution structure. The die is bonded to the first redistribution structure through flip-chip bonding. The conductive structures surround the die. The encapsulant encapsulates the die and the conductive structures. The second redistribution structure is disposed on the encapsulant and is electrically connected to the first redistribution structure through the conductive structures. The second redistribution structure includes at least one conductive pattern layer that is in physical contact with the encapsulant. Top surfaces of the conductive structures contacting the second redistribution structure are coplanar with a top surface of the encapsulant.

Integrated fan-out package, package-on-package structure, and manufacturing method thereof

Packaged devices and methods of manufacturing the devices are described herein. The packaged devices may be fabricated using heterogeneous devices and asymmetric dual-side molding on a multi-layered redistribution layer (RDL) structure. The packaged devices may be formed with a heterogeneous three-dimensional (3D) Fan-Out System-in-Package (SiP) structure having small profiles and can be formed using a single carrier substrate.

Semiconductor devices and methods of manufacturing

Package structure and method of fabricating the same

A semiconductor package and a method of manufacturing the same are provided. The semiconductor package includes a semiconductor die, an encapsulant and a redistribution structure. The encapsulant laterally encapsulates the semiconductor die. The redistribution structure is disposed on the encapsulant and electrically connected with the semiconductor die, wherein the redistribution structure comprises a first conductive via, a first conductive wiring layer and a second conductive via stacked along a stacking direction, the first conductive via has a first terminal surface contacting the first conductive wiring layer, the second conductive via has a second terminal surface contacting the first conductive wiring layer, an area of a first cross section of the first conductive via is greater than an area of the first terminal surface of the first conductive via, and an area of a second cross section of the second conductive via is greater than an area of the second terminal surface of the second conductive via.

Semiconductor package and method of manufacturing the same

A semiconductor package is provided. The semiconductor package includes an encapsulating layer, a semiconductor die formed in the encapsulating layer, and an interposer structure covering the encapsulating layer. The interposer structure includes an insulating base having a first surface facing the encapsulating layer, and a second surface opposite the first surface. The interposer structure also includes insulting features formed on the first surface of the insulating base and extending into the encapsulating layer. The insulting features are arranged in a matrix and face a top surface of the semiconductor die. The interposer structure further includes first conductive features formed on the first surface of the insulating base and extending into the encapsulating layer. The first conductive features surround the matrix of the plurality of insulting features.

Structures and formation methods of a package structure are provided. The method includes forming a conductive structure over a carrier substrate and disposing a semiconductor die over the carrier substrate. The method also includes pressing a protective substrate against the carrier substrate at an elevated temperature to bond the protective substrate to the conductive structure. The method further includes forming a protective layer to surround the semiconductor die.

Structure and formation method of package structure with fan-out structure

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Sanchong, Taiwan

Shih-Ting Hung