Taiwan Semiconductor Manufacturing Comp. Ltd.

Shih Pei Chou

Dun-Nian Yaung

Yeur-Luen Tu

Shu-Ting Tsai

Cheng-Hsien Chou

Sheng-Chau Chen

Jen-Cheng Liu

Feng-Chi Hung

Chia-Shiung Tsai

Ching-Chun Wang

Chih-Yu Lai

U-Ting Chen

Hsiao-Hui Tseng

Chia-Chieh Lin

Shyh-Fann Ting

Chih-Hui Huang

Shih-Chang Liu

Jiech-Fun Lu

Tzu-Hsuan Hsu

Jeng-Shyan Lin

Yen-Ting Chiang

Ching-Chung Su

Cheng-Ying Ho

Min-Feng Kao

Hung-Wen Hsu

Ming-Tsong Wang

Sin-Yao Huang

Chun-Han Tsao

Chun-Wei Chang

Yen-Chang Chu

Min-Ying Tsai

Wei-Cheng Hsu

Kai-Chun Hsu

Chih-Ta Chen

Szu-Ying Chen

Chun-Chieh Chuang

Sheng-Chan Li

Ju-Shi Chen

Hui-Wen Shen

Cheng-Ta Wu

Wen-De Wang

Yi-Shin Chu

Wen-I Hsu

Chun-Tsung Kuo

Chih-Chien Wang

Wei-Tung Huang

Yu-Hao Shih

Lin Chia-Chieh

A method includes performing an anisotropic etching on a semiconductor substrate to form a trench. The trench has vertical sidewalls and a rounded bottom connected to the vertical sidewalls. A damage removal step is performed to remove a surface layer of the semiconductor substrate, with the surface layer exposed to the trench. The rounded bottom of the trench is etched to form a slant straight bottom surface. The trench is filled to form a trench isolation region in the trench.

Deep trench isolations and methods of forming the same

A stacked integrated circuit (IC) device and a method are disclosed. The stacked IC device includes a first semiconductor element. The first substrate includes a dielectric block in the first substrate; and a plurality of first conductive features formed in first inter-metal dielectric layers over the first substrate. The stacked IC device also includes a second semiconductor element bonded on the first semiconductor element. The second semiconductor element includes a second substrate and a plurality of second conductive features formed in second inter-metal dielectric layers over the second substrate. The stacked IC device also includes a conductive deep-interconnection-plug coupled between the first conductive features and the second conductive features. The conductive deep-interconnection-plug is isolated by dielectric block, the first inter-metal-dielectric layers and the second inter-metal-dielectric layers.

Interconnect structure for stacked device

Some embodiments relate an integrated circuit (IC) including a first substrate including a plurality of imaging devices. A second substrate is disposed under the first substrate and includes a plurality of logic devices. A first interconnect structure is disposed between the first substrate and the second substrate and electrically couples imaging devices within the first substrate to one another. A second interconnect structure is disposed between the first interconnect structure and the second substrate, and electrically couples logic devices within the second substrate to one another. A bond pad structure is coupled to a metal layer of the second interconnect structure and extends along inner sidewalls of both the first interconnect structure and the second interconnect structure. An oxide layer extends from above the first substrate to below a plurality of metal layers of the first interconnect structure, and lines inner sidewalls of the bond pad structure.

Bond pad structure for bonding improvement

Some embodiments relate an integrated circuit (IC). The IC includes a first substrate including an array of photodetectors, wherein a bond pad opening extends through the first substrate and is defined by an inner sidewall of the first substrate. An interconnect structure is disposed over the first substrate and includes a plurality of metal layers stacked over one another and disposed within a dielectric structure. The bond pad opening further extends through at least a portion of the interconnect structure and is further defined by an inner sidewall of the interconnect structure. A bond pad structure directly contacts a metal layer of the plurality of metal layers in the interconnect structure and is located at an uppermost extent of the bond pad opening.

Some embodiments of the present disclosure relate to a method in which a functional layer is formed over an upper semiconductor surface of a semiconductor substrate, and a capping layer is formed over the functional layer. A first etchant is used to form a recess through the capping layer and through the functional layer. The recess has a first depth and exposes a portion of the semiconductor substrate there through. A protective layer is formed along a lower surface and inner sidewalls of the recess. A second etchant is used to remove the protective layer from the lower surface of the recess and to extend the recess below the upper semiconductor surface to a second depth to form a deep trench. To prevent etching of the functional layer, the protective layer remains in place along the inner sidewalls of the recess while the second etchant is used.

Deep trench isolation shrinkage method for enhanced device performance

An interconnect apparatus and a method of forming the interconnect apparatus is provided. Two substrates, such as wafers, dies, or a wafer and a die, are bonded together. A first mask is used to form a first opening extending partially to an interconnect formed on the first wafer. A dielectric liner is formed, and then another etch process is performed using the same mask. The etch process continues to expose interconnects formed on the first substrate and the second substrate. The opening is filled with a conductive material to form a conductive plug.

3DIC interconnect apparatus and method

Some embodiments relate to a method. In the method, a CMOS substrate, which includes a plurality of CMOS devices, is received. An interconnect structure including a plurality of metal layers is formed over the CMOS substrate, wherein a first metal layer of the metal layers is nearest the CMOS substrate and an Nth of the metal layers is furthest from the CMOS substrate. An image sensor substrate is bonded to the interconnect structure. A first mask is formed over the image sensor substrate, and a first etch is performed with the first mask in place to expose an upper surface of the first metal layer. A conductive bond pad material is formed in direct contact with the exposed first metal layer.

An interconnect apparatus and a method of forming the interconnect apparatus is provided. Two integrated circuits are bonded together. A first opening is formed through one of the substrates. A multi-layer dielectric film is formed along sidewalls of the first opening. One or more etch processes form one or more spacer-shaped structures along sidewalls of the first opening. A second opening is formed extending from the first opening to pads in the integrated circuits. A dielectric liner is formed, and the opening is filled with a conductive material to form a conductive plug.

An image sensor includes a sensor portion and an ASIC portion bonded to the sensor portion. The sensor portion includes a first substrate having radiation-sensing pixels, a first interconnect structure, a first isolation layer, and a first dielectric layer. The ASIC portion includes a second substrate, a second isolation layer, and a second dielectric layer. The material compositions of the first and second isolation layers and the first and second dielectric layers are configured such that the first and second isolation layers may serve as barrier layers to prevent copper diffusion into oxide. The first and second isolation layers may also serve as etching-stop layers in the formation of the image sensor.

Stacked image sensor having a barrier layer

A representative device includes a patterned opening through a layer at a surface of a device die. A liner is disposed on sidewalls of the opening and the device die is patterned to extend the opening further into the device die. After patterning, the liner is removed. A conductive pad is formed in the device die by filling the opening with a conductive material.

Conductive pad structure for hybrid bonding and methods of forming same

An apparatus comprises a first semiconductor chip including a first substrate, a plurality of first inter-metal dielectric layers and a plurality of first metal lines, a second semiconductor chip having a surface in contact with a surface of the first semiconductor chip, wherein the second semiconductor chip comprises a second substrate, a plurality of second inter-metal dielectric layers and a plurality of second metal lines and a conductive plug coupled between the first metal lines and the second metal lines, wherein the conductive plug comprises a first portion over a first side of a hard mask layer and a second portion over a second side of the hard mask layer, wherein the hard mask layer is a ring-shaped layer, and wherein the conductive plug is formed in a center opening of the ring-shaped layer.

Interconnect apparatus and method

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Tainan, Taiwan

Shih Pei Chou