Taiwan Semiconductor Manufacturing Comp. Ltd.

Shih-Kuang Hsiao

Kong-Beng Thei

Chen-Liang Chu

Yi-Sheng Chen

Fei-Yuh Chen

Chun Lin Tsai

Fei-Yun Chen

A transistor includes an isolation region surrounding an active region. The transistor also includes a gate dielectric layer over a portion of the active region. The transistor further includes a gate electrode over the gate dielectric layer. The portion of the active region under the gate dielectric layer includes a channel region between a drain region and a source region, and at least one wing region adjoining the channel region. The at least one wing region has a base edge adjoining the channel region. The at least one wing region is polygonal or curved.

Transistor having a wing region

An integrated circuit and a method of forming is provided. The method includes forming a first well in a substrate, the first well having a first conductivity type, and forming a first source/drain region in the first well, the first source/drain region having a second conductivity type. A resistance protection ring is formed on the substrate.

High voltage drain-extended MOSFET having extra drain-OD addition

A semiconductor device includes an active region having a channel region and at least a wing region adjoining the channel region under the gate dielectric layer. The at least one wing region may be two symmetrical wing regions across the channel region.

Transistor having an active region with wing structure

An integrated circuit includes a high-voltage well having a first doping type, a first doped region and a second doped region embedded in the high-voltage well, the first and second doped regions having a second doping type and spaced apart by a channel in the high-voltage well, source/drain regions formed in the first doped region and in the second doped region, each of the source/drain regions having the second doping type and more heavily doped than the first and second doped regions, first isolation regions spaced apart from each of the source/drain regions, and resistance protection oxide forming a ring surrounding each of the source/drain regions.

Presented herein is a field effect transistor device, optionally a lateral power transistor, and a method for forming the same, comprising providing a substrate, creating a doped buried layer, and creating a primary well in the substrate on the buried layer. A drift drain may be created in the primary well and a counter implant region implanted in the primary well and between the drift drain and the buried layer. The primary well may comprise a first and second implant region with the second implant region at a depth less than the first. The counter implant may be at a depth between the first and second implant regions. The primary well and counter implant region may comprise dopants of the same conductivity type, or both p+-type dopants. A gate may be formed over a portion of a drift drain.

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Hsin-Chu, Taiwan

Shih-Kuang Hsiao