United Microelectronics Corp.

Shih-Hung Tsai

Jyh-Shyang Jenq

Li-Wei Feng

Chien-Ting Lin

Ssu-I Fu

Chao-Hung Lin

Ying-Tsung Chen

Chun-Hsien Lin

Po-Kuang Hsieh

Hon-Huei Liu

Chih-Kai Hsu

Shih-Fang Hong

Wen-Tai Chiang

Yu-Hsiang Hung

Chih-Wei Chen

Ching-Wen Hung

Tong-Jyun Huang

En-Chiuan Liou

Chin-Fu Lin

Jia-Rong Wu

Nan-Yuan Huang

Yu-Ting Tseng

Kuan-Hao Tseng

Chin-Cheng Chien

Chih-Sen Huang

An-Chi Liu

Rai-Min Huang

Chien-Liang Lin

Chen-Hua Tsai

Cheng-Ping Kuo

Teng-Chun Tsai

Yu-Cheng Tung

Yi-Wei Chen

Chih-Chien Liu

Chun-Yuan Wu

Chi-Mao Hsu

Chih-Wei Yang

Yi-Hui Lee

Yu-Shu Lin

Ying-Cheng Liu

Hsuan-Hsu Chen

YI-Fan Li

Ying-Chih Lin

Tien-Chen Chan

Shao-Wei Wang

Cheng-Tzung Tsai

Chia-Hsun Tseng

Chih-Chung Chen

Yi-Kuan Wu

Kun-Hsin Chen

Po-Chang Lin

Bo-Han Huang

Ching-Yu Chang

Yu-Ren Wang

Chun-Hsien Huang

Yu-Hsiang Lin

Chen-Ming Huang

I-Ming Tseng

Hsin-Yu Chen

Chia-Lin Lu

Shou-Wei Hsieh

Yi-Wen Chen

Ching-Ling Lin

Chiu-Hsien Yeh

Ying-Wei Yen

Chun-Hao Lin

Chun-Yao Yang

Ted Ming-Lang Guo

Li-Chiang Chen

Chih-Hsien Tang

Chia-Ching Lin

Yao-Jen Fan

Sheng-Huei Dai

Ming-Shiou Hsieh

Rong-Sin Lin

Te-Lin Sun

Chih-Wei Wu

Yi-Ren Chen

Chorng-Lih Young

Mei-Chen Chen

Kai-Ping Wang

Chueh-Fei Tai

A method for fabricating a surface acoustic wave (SAW) device includes the steps of forming a first dielectric layer on a substrate, forming a piezoelectric layer on the first dielectric layer, forming a second dielectric layer on the piezoelectric layer, performing a photo-etching process to remove the second dielectric layer for forming a recess in the second dielectric layer, forming a metal layer in the recess, and then performing a planarizing process to remove the metal layer for forming an electrode in the recess.

Surface acoustic wave device and method for fabricating the same

A nanowire transistor includes a channel structure on a substrate, a gate structure on and around the channel structure, a source/drain structure adjacent to two sides of the gate structure, and a contact plug connected to the source/drain structure. Preferably, the source/drain structure includes graphene and the contact plug further includes a silicide layer on the source/drain structure, a graphene layer on the silicide layer, and a barrier layer on the graphene layer.

Nanowire transistor and method for fabricating the same

A method for fabricating a surface acoustic wave (SAW) device includes the steps of forming a buffer layer on a substrate, forming a high velocity layer on the buffer layer, forming a medium velocity layer on the high velocity layer, forming a low velocity layer on the medium velocity layer, forming a piezoelectric layer on the low velocity layer, and forming an electrode on the piezoelectric layer. Preferably, the buffer layer includes silicon oxide, the high velocity layer includes graphene, the medium velocity layer includes silicon oxynitride, and the low velocity layer includes titanium oxide.

A method for fabricating a semiconductor device includes the steps of forming a first inter-metal dielectric (IMD) layer on a substrate, forming a first trench and a second trench in the first IMD layer, forming a bottom electrode in the first trench and the second trench, forming a ferroelectric (FE) layer on the bottom electrode, and then forming a top electrode on the FE layer to form a ferroelectric random access memory (FeRAM).

Semiconductor device and method for fabricating the same

A method for fabricating a semiconductor device includes the steps of forming a metal-oxide semiconductor (MOS) transistor on a substrate, forming an interlayer dielectric (ILD) layer on the MOS transistor, forming a ferroelectric field effect transistor (FeFET) on the ILD layer, and forming a ferroelectric random access memory (FeRAM) on the ILD layer. The formation of the FeFET further includes first forming a semiconductor layer on the ILD layer, forming a gate structure on the semiconductor layer, and then forming a source/drain region adjacent to the gate structure.

A method for fabricating a nanowire transistor includes the steps of first forming a nanowire channel structure on a substrate, in which the nanowire channel structure includes first semiconductor layers and second semiconductor layers alternately disposed over one another. Next, a gate structure is formed on the nanowire channel structure and then a source/drain structure is formed adjacent to the gate structure, in which the source/drain structure is made of graphene.

A high electron mobility transistor includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer. The composition of the first III-V compound layer and the second III-V compound layer are different from each other. A shallow recess, a first deep recess and a second deep recess are disposed in the second III-V compound layer. The first deep recess and the second deep recess are respectively disposed at two sides of the shallow recess. The source electrode fills in the first deep recess and contacts the top surface of the first III-V compound layer. A drain electrode fills in the second deep recess and contacts the top surface of the first III-V compound layer. The shape of the source electrode and the shape of the drain electrode are different from each other. A gate electrode is disposed on the shallow recess.

HEMT and method of fabricating the same

A method for fabricating semiconductor device includes the steps of: forming fin-shaped structures on a substrate; using isopropyl alcohol (IPA) to perform a rinse process; performing a baking process; and forming a gate oxide layer on the fin-shaped structures. Preferably, a duration of the rinse process is between 15 seconds to 60 seconds, a temperature of the baking process is between 50&#xb0; C. to 100&#xb0; C., and a duration of the baking process is between 5 seconds to 120 seconds.

Rinse process after forming fin-shaped structure

A single photon avalanche diode includes a silicon-on-insulator (SOI) substrate having a base substrate, a buried oxide layer over the base substrate, and a silicon layer over the buried oxide layer. At least one photodiode region is disposed in the base substrate. The photodiode region comprises an epitaxial layer embedded in the base substrate.

Single photon avalanche diode fabricated on a silicon-on-insulator substrate

A semiconductor device includes: a substrate having a first region and a second region; a first fin-shaped structure on the first region and a second fin-shaped structure on the second region, wherein each of the first fin-shaped structure and the second fin-shaped structure comprises a top portion and a bottom portion; a first doped layer around the bottom portion of the first fin-shaped structure; a second doped layer around the bottom portion of the second fin-shaped structure; a first liner on the first doped layer; and a second liner on the second doped layer.

Semiconductor device

A high electron mobility transistor includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer. The composition of the first III-V compound layer and the second III-V compound layer are different from each other. A shallow recess, a first deep recess and a second deep recess are disposed in the second III-V compound layer. The first deep recess and the second deep recess are respectively disposed at two sides of the shallow recess. The source electrode fills in the first deep recess and contacts the top surface of the first III-V compound layer. A drain electrode fills in the second deep recess and contacts the top surface of the first III-V compound layer. The shape of the source electrode and the shape of the drain electrode are different from each other. A gate electrode is disposed directly on the shallow recess.

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Tainan, Taiwan

Shih-Hung Tsai