Sandisk Technologies Inc.

Sandisk Corporation

Shih-Chung Lee

Gerrit Jan Hemink

Ken Oowada

Deepanshu Dutta

Toru Miwa

Chun-Hung Lai

Dana Lee

Yingda Dong

Jun Wan

Yupin K Fong

Anubhav Khandelwal

Guirong Liang

Masaaki Higashitani

Jeffrey W Lutze

Huai-Yuan Tseng

Henry Chin

Liang Li

Jiahui Yuan

Ching-Huang Lu

Ming Hsi Wang

Takashi Murai

Shinji Sato

Rajdeep Gautam

Arash Hazeghi

Wenzhou Chen

Genki Sano

Cheng-Kuan Yin

Hironobu Nakao

The storage device that includes a non-volatile memory with a control circuitry that is communicatively coupled to an array of memory cells that are arranged in a plurality of word lines. The control circuitry is configured to program the memory cells in a plurality of programming loops. The programming loops include applying a programming pulse to a selected word line of the plurality of word lines. The programming loops also include applying a verify pulse Vto the selected word line to simultaneously verify a lower tail of the memory cells being programmed to a data state N and an upper tail of the memory cells that have been programmed to a data state N&#x2212;1. The data state N&#x2212;1 has a lower voltage threshold than the data state N.

Systems and methods for detecting erratic programming in a memory system

A method for operating non-volatile storage disclosed herein. The method comprises performing an operation on a set of non-volatile storage elements. The operation on the set of non-volatile storage elements includes providing temperature compensation based on an operation temperature of the set of non-volatile storage elements. The providing temperature compensation includes determining if the operation temperature is outside a temperature range where constant compensation is valid and applying the temperature compensation based on the determination.

Non-linear temperature compensation for wider range operation temperature products

For a non-volatile memory die formed of multiple blocks of memory cells, the memory die has a multi-bit bad block flag for each block stored on the memory die, such as in a fuse ROM. For each block, the multi-bit flag indicates if the block has few defects and is of the highest reliability category, is too defective to be used, or is in of one of multiple recoverability categories. The multi-bit bad blocks values can be determined as part a test process on fresh devices, where the test of a block can be fail stop for critical category errors, but, for recoverable categories, the test continues and tracks the test results to determine a recoverability category for the block and write this onto the die as a bad block flag for each block. These recoverability categories can be incorporated into wear leveling operations.

Block quality classification at testing for non-volatile memory, and multiple bad block flags for product diversity

Apparatuses and techniques are described for reducing charge loss in a select gate transistor in a memory device. In one aspect, a dummy memory cell adjacent to a select gate transistor is weakly programmed during an erase operation by applying a program pulse to the dummy memory cell. The program pulse can be applied after an erase bias is applied to the memory cells and before an erase-verify test is performed, in one approach. The program pulse can be applied during the setup of the voltages for the erase-verify test. The magnitude of the program pulse can be increased in successive erase loops of an erase operation as the magnitude of a substrate voltage is also increased. The magnitude of the program pulse can also be set as an increasing function of a number of program-erase (P-E) cycles.

Programming dummy memory cells in erase operation to reduce threshold voltage downshift for select gate transistors

A non-volatile memory system comprises a plurality of memory cells arranged in a three dimensional structure and one or more control circuits in communication with the memory cells. The one or more control circuits are configured to program and verify programming for the memory cells. The verifying programming of the plurality of memory cells includes verifying programming for a first data state using a verify operation for a second data state. In one embodiment, the one or more control circuits are also configured to sense whether different memory cells of the plurality of memory cells are in different data states by applying different bit line voltages to the different memory cells.

Non-volatile memory with prior state sensing

A non-volatile memory system utilizes partial block erasing during program operations to mitigate the effects of programming pass voltage disturbances. A programming request is received that is associated with a group of word lines from a block, such as all or a portion of the word lines. The system erases and soft programs the block prior to beginning programming. The system programs a subset of the word lines of the block for the programming request. After programming the subset of word lines, the system pauses the programming operation and performs an erase operation for the unprogrammed word lines of the block. The already programmed word lines and one or more optional buffer word lines may be inhibited from erasing during the erase operation. After erasing the unprogrammed word lines, the system completes the programming request by programming the remaining user data in the unprogrammed region of the block.

Partial block erase for block programming in non-volatile memory

When erasing non-volatile storage, a verification process is used between erase operations to determine whether the non-volatile storage has been successfully erased. The verification process includes separately performing verification for different subsets of the non-volatile storage elements.

Verification process for non-volatile storage

A method and non-volatile storage system are provided in which the voltage applied to the source end of a NAND string depends on the location of the non-volatile storage element that is selected for sensing. This may be done without body-biasing the NAND string. Having the magnitude of the voltage applied to the source end of a NAND string depend on the location of the selected memory cell (without any body biasing) helps to mitigate failures that are dependent on which word line is selected during a sensing operation of one embodiment. Additionally, the magnitude of a read pass voltage may depend on either the source line voltage or the location of the selected memory cell.

Compensating source side resistance versus word line

Reducing peak current and/or power consumption during erase verify of a non-volatile memory is disclosed. During an erase verify, memory cells are verified at a strict reference level that is deeper (e.g., lower threshold voltage) than a target reference level. After the strict erase verify, strings of memory cells that pass the strict erase verify are locked out from a next erase verify at the target reference level. Locked out strings do not conduct a significant current during erase verify, thus reducing peak current and/or power consumption.

Erase verify in non-volatile memory

A system for programming non-volatile storage is proposed that reduces the impact of interference from the boosting of neighbors. Memory cells are divided into two or more groups. In one example, the memory cells are divided into odd and even memory cells; however, other groupings can also be used. Prior to a first trigger, a first group of memory cells are programmed together with a second group of memory cells using a programming signal that increases over time. Subsequent to the first trigger and prior to a second trigger, the first group of memory cells are programmed separately from the second group of memory cells using a programming signal that has been lowered in magnitude in response to the first trigger. Subsequent to the second trigger, the first group of memory cells are programmed together with the second group of memory cells with the programming signal being raised in response to the second trigger. Before and after both triggers, the first group of memory cells are verified together with the second group of memory cells.

Programming non-volatile storage including reducing impact from other memory cells

Reducing peak current and/or power consumption during verify of a non-volatile memory is disclosed. During a program verify, only memory cells in a first physical segment of the selected word line are verified during an initial program loop; memory cells in a different physical segment of the word line are locked out and not verified. The locked out memory cells may be slower to program. During a later program loop, memory cells in all physical segments are program verified. Locked out strings do not conduct a significant current during verify, thus reducing current/power consumption.

Reduced current program verify in non-volatile memory

Improving endurance for non-volatile memory by dynamic erase depth is disclosed. A group of memory cells are erased. Then, at least some of the erased memory cells are programmed. Programming the memory cells typically impacts the erase threshold distribution of those memory cells that were intended to stay erased. The erase depth of the next erase can be adjusted based on how the program operation affects the erase threshold distribution. As one example, the upper tail of the erase distribution is measured after programming. The higher the upper tail, the shallower the next erase, in one embodiment. This helps to improve endurance. In one embodiment, the erase depth is adjusted by determining a suitable erase verify level. Rather than (or in addition to) adjusting the erase verify level, the number of erase pulses that are performed after erase verify passes can be adjusted to adjust the erase depth.

Dynamic erase depth for improved endurance of non-volatile memory

Methods and devices for charging unselected bit lines are disclosed. The rate at which inhibited (or unselected) bit lines are charged may depend on a program condition. The program condition may be completion of a program loop. As another example, the program condition may be a certain program state completing or nearly completing programming. As one example, the bit lines may be charged at a faster rate prior to the program condition occurring than after the program condition. As another example, the bit lines may be charged at a slower rate prior to the program condition than after the program condition. Charging the unselected bit lines at a slower rate may reduce current consumption. Charging the unselected bit lines at a faster rate may allow for faster programming.

Program condition dependent bit line charge rate

A set of memory cells can be erased by individually erasing portions of the set in order to normalize the erase behavior of each memory cell and provide more consistent erase rates. An erase voltage pulse can be applied to the set of memory cells with a first group of cells biased for erase and a second group biased to inhibit erase. The erase depth is made shallower as the device is cycled more.

Partitioned erase and erase verification in non-volatile memory

A system for reducing read disturb on edge word lines in non-volatile storage is disclosed. In one embodiment, the memory cells on edge word lines are programmed using a series of pulses that have an initial magnitude and step size between pulses that are lower than for memory cells on word lines that are not edge word lines. Additionally, when reading memory cells on word lines that are not edge word lines, the edge word lines receive a lower pass voltage than the default pass voltage applied to other unselected word lines. In another embodiment. the system applies a higher than normal bias on a neighboring word lines when reading memory cells on an edge word line.

Growing community of inventors

Yokohama, Japan

Shih-Chung Lee