United Microelectronics Corp.

Shih-Chanh Chang

Water Lur

Chein-Cheng Wang

Cheng-Han Huang

Hong-Tsz Pan

Jiun Y Wu

Ming-Tzung Yang

Der Yuan Wu

Liang-Chih Lin

The present invention is a method of fabricating interconnects. A semiconductor substrate having a dielectric layer is provided. The dielectric layer has a via opening therein, which exposes the semiconductor substrate. Next, the surfaces of the via opening is covered with a conformal titanium layer formed by a sputtering process. The surface of the conformal titanium layer is covered with an Al&mdash;Si&mdash;Cu alloy layer formed by a sputtering process at a temperature of about 0&deg; C. to 200&deg; C. Then, the surface of the Al&mdash;Si&mdash;Cu alloy layer is covered with an Al&mdash;Cu alloy layer formed by a sputtering process at a temperature of about 380&deg; C. to 450&deg; C., which Al&mdash;Cu alloy layer fills the via opening. The Al&mdash;Cu alloy layer, the Al&mdash;Si&mdash;Cu alloy layer and the wetting layer on the dielectric layer are patterned by photolithography and etching process.

Method of fabricating vias

A method of fabricating a glue layer and a barrier layer. A Ti layer is formed with a collimator sputtering in the via opening or the contact opening of the substrate. Through the control of flow of N,and Ar, a nitride mode TiN,layer is formed on the Ti layer by sputtering. The nitride mode TiN,layer and the Ti layer uncovered by the nitride mode TiN,layer are treated with N,RF plasma. This strengthens the structure of the nitride mode TiN,layer and allows the reaction with the exposed Ti layer so that it is transformed into a TiN,layer.

Fabricating method of glue layer and barrier layer

A new method of forming a metal diffusion barrier layer is described. Semiconductor device structures are formed in and on a semiconductor substrate. At least one dielectric layer covers the semiconductor structures and at least one contact hole has been opened through the dielectric layer(s) to the semiconductor substrate. A metal diffusion barrier layer is now formed using the following steps: In the first step, a thin layer of titanium is deposited conformally over the surface of the dielectric layer(s) and within the contact opening(s) and annealed in a nitrogen atmosphere at a temperature of between about 580.degree. to 630.degree. C. for between about 20 to 120 seconds. The second step is to form stable and adhesive titanium compounds on the pre-metal dielectric layer as well as to form a low resistance silicide on the contact silicon by annealing at between about 800.degree. to 900.degree. C. for between about 5 to 60 seconds. The final step is to release the system stress by tempering the layer at a temperature of between about 600.degree. to 750.degree. C. This completes the barrier layer which has good adhesion to the dielectric layer(s) and, therefore, promotes improved pad bonding yield.

Method of making a reliable barrier layer

A new method of forming the dielectric layer of an integrated circuit is described. A thick insulating layer is formed over semiconductor device structures in and on a semiconductor substrate. A first metal layer is deposited over the thick insulating layer. The first metal layer is etched using conventional photolithography and etching techniques to form the desired metal pattern on the surface of the thick insulating layer. The intermetal dielectric layer is formed by first covering the patterned first metal layer with a layer of silicon oxide. The silicon oxide layer is covered with a layer of spin-on-glass material which is baked and cured. A second layer of silicon oxide completes the intermetal dielectric layer. Via openings are formed through the intermetal dielectric layer to the underlying patterned first metal layer. A silicon nitride cap is formed on the exposed surfaces of the spin-on-glass layer within the via openings to prevent outgassing from the intermetal dielectric layer, and thus to prevent poisoned via metallurgy. A second metal layer is deposited overlying the intermetal dielectric layer and within the via openings and fabrication of the integrated circuit is completed.

Via sidewall SOG nitridation for via filling

A method of metallization using a tungsten plug is described. A contact hole is opened to the semiconductor substrate through an insulating layer covering semiconductor structures in and on the semiconductor substrate. A glue layer is deposited conformally over the surface of the insulating layer and within the contact opening. A tungsten plug is formed within the contact opening. The glue layer is removed except for portions of the glue layer underneath the tungsten plug and on the lower sides of the tungsten plug. Ditches are left on the upper sides of the tungsten plug where the glue layer has been removed. The ditches around the tungsten plug are filled with a dielectric material. A second metallization is deposited and patterned. The patterned second metallization does not extend over one side portion of the tungsten plug; that is, there is no dog-bone formation. There is no junction damage through the side portion of the tungsten plug not covered by the second metallization because the dielectric material filling the ditches protects the glue layer from being etched away. In a second embodiment of the invention, after the contact hole is opened, the insulating layer is reflowed forming an overhang around the contact hole. A glue layer is deposited conformally over the surface of the insulating layer and within the contact opening. A tungsten plug is formed within the contact opening.

Growing community of inventors

Taichung, Taiwan

Shih-Chanh Chang