Hitachi, Ltd.

Hitachi-High-Technologies Corporation

Renesas Technology Corp.

Shigeya Tanaka

Takashi Hotta

Masahiro Iwamura

Hideo Maejima

Yasuhiro Nakatsuka

Tadaaki Bandoh

Kazuo Kato

Kozaburo Kurita

Sin-ichi Sinoda

Hideo Sawamoto

Kotaro Shimamura

Tetsuo Nakano

Koji Saito

Tatsumi Yamauchi

Kenichi Kurosawa

Toshihiko Kurihara

Akiyoshi Osumi

Takashi Hiroi

Kazutaka Mori

Masahiko Saito

Shoji Yoshida

Hiroshi Miyai

Yasuhiro Gunji

Yoshiki Kobayashi

Dai Fujii

Atsushi Ichige

Takeshi Takemoto

Michio Nakano

Takako Fujisawa

Yoshiyuki Momiyama

Kazuya Hayashi

Ichiro Kawashima

Hiroshi Kawaguchi

Hiromichi Yamada

Ikuro Masuda

Noboru Akiyama

Takashi Akioka

Kei Shimura

Masaki Hasegawa

Kenji Aiko

Hirohito Okuda

Tetsuya Shimomura

Yasuko Aoki

Kenji Jin

Tatsuo Nojiri

Hisashi Tada

The present invention provides a device for detecting foreign matter and a method for detecting foreign matter to detect a foreign matter on a surface of an object such as a film of an electrode mixture etc. or a foreign matter contained in the object, thereby to improve the reliability of the object. By irradiating an object with a terahertz illumination light(wavelength of 4 &#x3bc;m to 10 mm) and detecting a scattered lightfrom an electrodeas an example of the object by a scattered light detector, a foreign matter on a surface of the electrodeor contained in the electrode, for example, a metal foreign matter, is detected. The electrodeis one in which electrode mixture layerseach including an active material, conductive additive and a binder as components are coated on both surfaces of a collector. The scattered lightresults from a part of a transmitted lightreflected by the metal foreign matter

Device for detecting foreign matter and method for detecting foreign matter

A visual inspection apparatus and method using the scanning electron microscope are disclosed. An electron beam is scanned repeatedly on a sample, and an inspection and a reference image are generated by the secondary electrons generated from the sample or reflected electrons. From the differential image between the inspection image and the reference image, a defect is determined. The number of pixels in the generated image along the direction of repetitive scanning by the electron beam can be changed.

Inspection apparatus and inspection method using electron beam

An image processing apparatus for wafer inspection tool that is able to perform continuously cell to cell comparison inspection, die to die comparison inspection, and cell-to-cell and die-to-die hybrid comparison inspection, employing a plurality of processors. This image processing apparatus for wafer inspection tool comprises a plurality of processors for performing parallel processing, means for cutting out image data including a forward end overlap and a rear end overlap at partition boundaries in order to cut serial data into a predetermined image size, means for distributing the cutout image data to the plurality of processors, and means for assembling results of processing performed by the plurality of processors. The forward end overlap is set greater than a pitch of the cell subject to cell to cell comparison inspection.

Image processing unit for wafer inspection tool

The present invention provides a mirror electron projection (MPJ) type (SEPJ type included) scanning electron beam apparatus that is capable of performing condition setup, and a method and apparatus for inspecting pattern defects with the scanning electron beam apparatus. A mirror electron projection type defect inspection apparatus, which comprises a charging device for emitting a charging electron beam, electron beam irradiation means for shedding a mirror electron projection electron beam onto an inspection region near which an electrical potential distribution is formed, detection means for detecting secondary electrons or reflected electrons generated from a surface and proximity of the specimen, and defect detection means for detecting a defect by processing a mirror image signal that is detected by the detection means, includes irradiation condition optimization means for optimizing charging electron beam irradiation conditions.

Method and apparatus for inspecting pattern defects and mirror electron projection type or multi-beam scanning type electron beam apparatus

The data processor for executing, instructions realized by wired logic, by a pipeline system, includes a plurality of instruction registers, and arithmetic operation units of the same number. A plurality of instructions read in the instruction registers in one machine cycle at a time are processed in parallel by the plurality of arithmetic operation units.

Data processor

A data processor has a first cache memory with a large capacity and one port and a second cache memory with a small capacity and two ports disposed between a main memory and an instruction processing section. Data which is frequently used is stored in the first cache memory and data which is less frequently used is stored in the second cache memory under control of a controller responsive to prefetch instructions. One of the cache memories may be a set associative cache memory composed of a plurality of memory chips each having at least two memory banks and an output part to gain access to data sets consecutively and one at a time within the memory banks. On the basis of an address sent from the instruction processing section, a memory bank is selected, and a data set from the selected memory bank is supplied to the processing section.

Data processor having cache memory

An information processing system having an original clock oscillator for delivering at least one original clock signal K defined as a first clock signal and a plurality of information processing units supplied with the original clock signal K, wherein each information processing unit comprises clock generating means for generating at least one second clock signal Kwhich is phase-locked with the original clock signal K and which has a predetermined duty cycle and a logic device whose operation timing is controlled by the second clock signal Kand the operation timing of an interface provided between at least one pair of logic devices is synchronously controlled by the clock signal K.

Information processor and information processing system utilizing interface for synchronizing clock signal

An information processing system having an original clock oscillator for delivering at least one original clock signal K defined as a first clock signal and a plurality of information processing units supplied with the original clock signal K, wherein each information processing unit comprises clock generating means for generating at least one second clock signal K which is phase-locked with the original clock signal K and which has a predetermined duty cycle and a logic device whose operation timing is controlled by the second clock signal K , And the operation timing of an interface provided between at least one pair oflogic devices is synchronously controlled by the clock signal K .

Data processing system generating clock signal from an input clock, phase locked to the input clock and used for clocking logic devices

In semiconductor integrated circuit device and microprocessor including at least one functional circuit block, the start of operation of the functional circuit block is detected prior to the start of operation, the functional circuit block for which the start of operation has been detected is activated prior to the start of operation and inactivated after the termination of operation.

Low power consumption semiconductor integrated circuit device and microprocessor

A high speed, high performance pipelined semiconductor device is provided, such as a pipelined data processing device and memory device. In the pipeline operation, a functional circuit unit and a transmission unit are separately controlled at each pipeline stage cycle. A transmission unit between two functional circuit units is divided into N transmission units while considering a cycle time, and each divided transmission unit is assigned one pipeline stage cycle.

Pipelined semiconductor devices suitable for ultra large scale integration

Data processor with variable types of cache memories and a controller for selecting a cache memory to be access

Growing community of inventors

Hitachi, Japan

Shigeya Tanaka